PIC18F2221-I/ML Microchip Technology, PIC18F2221-I/ML Datasheet - Page 274

• Manufacturer Part Number: PIC18F2221-I/ML
• Description: IC PIC MCU FLASH 2KX16 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2221-I/ML

• Core Size: 8-Bit
• Program Memory Size: 4KB (2K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Package: 28QFN EP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 25
• Interface Type: I2C/SPI/USART
• On-chip Adc: 10-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2221/2321/4221/4321 FAMILY
24.5
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC
The user program memory is divided into three blocks.
One of these is a boot block of variable size. The
remainder of the memory is divided into two blocks on
binary boundaries.
FIGURE 24-5:
DS39689F-page 274
®
devices.
Boot Block
2K words
1K word
1K word
11/10
Block 0
Block 1
Program Verification and
Code Protection
Unimplemented
(PIC18FX321)
Reads all ‘0’s
1.5K words
Boot Block
512 words
2K words
8 Kbytes
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2221/2321/4221/4321
FAMILY DEVICES
Block 0
Block 1
01
MEMORY SIZE/DEVICE
1.75K words
BBSIZ<1:0>
Boot Block
256 words
2K words
Block 0
Block 1
00
11/10/01
0.5K words
Boot Block
512 words
1K word
Block 0
Block 1
Unimplemented
(PIC18FX221)
Reads all ‘0’s
4 Kbytes
Each of the three blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 24-5 shows the program memory organization
for 4 and 8-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 24-3.
0.75K words
Boot Block
256 words
1K word
Block 0
Block 1
00
000000h
0001FFh
000200h
0003FFh
000400h
0007FFh
000800h
000FFFh
001000h
001FFFh
002000h
1FFFFFh
Address
Range
© 2009 Microchip Technology Inc.
(Unimplemented Memory
Block Code Protection
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
Controlled By:
Space)