PIC24FJ32GA102-I/SO Microchip Technology, PIC24FJ32GA102-I/SO Datasheet
PIC24FJ32GA102-I/SO
Specifications of PIC24FJ32GA102-I/SO
Related parts for PIC24FJ32GA102-I/SO
PIC24FJ32GA102-I/SO Summary of contents
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... PIC24FJ64GA104 Family © 2009 Microchip Technology Inc. 28/44-Pin, 16-Bit Flash Microcontrollers with nanoWatt XLP Technology Preliminary Data Sheet General Purpose DS39951B ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Microchip Technology Inc. PIC24FJ64GA104 FAMILY Special Microcontroller Features (continued): • Flash Program Memory: - 10,000 erase/write cycle endurance (minimum) - 20-year data retention minimum - Selectable write protection boundary • Fail-Safe Clock Monitor Operation: - Detects clock failure and switches to on-chip FRC Oscillator • ...
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... Programmable, 32-Bit Cyclic Redundancy Check (CRC) Generator • Configurable Open-Drain Outputs on Digital I/O Pins • External Interrupt Sources MCLR AN9/C3INA/RP15/CN11/PMCS1/RB15 3 26 AN10/C3INB/CVREF/RTCC/RP14/CN12/PMWR/RB14 AN11/C1INC/RP13/CN13/PMRD/REFO/RB13 AN12/RP12/CN14/PMD0/RB12 6 23 PGEC2/TMS/RP11/CN15/PMD1/RB11 PGED2/TDI/RP10/CN16/PMD2/RB10 CAP DDCORE DISVREG 10 19 TDO/RP9/SDA1/CN21/PMD3/RB9 11 18 TCK/RP8/SCL1/CN22/PMD4/RB8 RP7/INT0/CN23/PMD5/RB7 PGC3/EMUC3/RP6/ASCL1 Preliminary ® (2) /CN24/PMD6/RB6 © 2009 Microchip Technology Inc. ...
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... OSCO/CLKO/CN29/PMA0/RA3 Legend: RPn represents remappable peripheral pins. Note 1: Gray shading indicates 5.5V tolerant input pins. 2: Alternative multiplexing for SDA1 and SCL1 when the I2C1SEL bit is set. 3: The back pad on QFN devices should be connected to V © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY ...
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... Alternative multiplexing for SDA1 and SCL1 when the I2C1SEL bit is set. 3: The back pad on QFN devices should be connected to V DS39951B-page 4 SOSCI/C1IND/RP4/CN1/RB4 33 1 TDO/PMA8/RA8 32 2 OSCO/CLKO/CN29/RA3 31 3 OSCI/CLKI/C1IND/CN30/RA2 PIC24FJXXGA104 AN8/RP18/PMA2/CN10/RC2 27 7 AN7/RP17/CN9/RC1 8 26 AN6/RP16/CN8/RC0 9 25 AN5/C1INA/RP3/SCL2/CN7/RB3 AN4/C1INB/RP2/SDA2/CN6/RB2 Preliminary © 2009 Microchip Technology Inc. ...
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... Electrical Characteristics .......................................................................................................................................................... 259 29.0 Packaging Information.............................................................................................................................................................. 277 Appendix A: Revision History............................................................................................................................................................. 287 The Microchip Web Site ..................................................................................................................................................................... 295 Customer Change Notification Service .............................................................................................................................................. 295 Customer Support .............................................................................................................................................................................. 295 Reader Response .............................................................................................................................................................................. 296 Product Identification System ............................................................................................................................................................ 297 © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Preliminary DS39951B-page 5 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39951B-page 6 Preliminary © 2009 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC24FJ32GA102 • PIC24FJ32GA104 • PIC24FJ64GA102 • PIC24FJ64GA104 The PIC24FJ64GA104 family provides an expanded peripheral feature set and a new option for high-performance applications which may need more than an 8-bit platform, but do not require the power of a digital signal processor ...
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... This information is provided in the pinout diagrams in the beginning of this data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first. Preliminary the pin features available on the © 2009 Microchip Technology Inc. ...
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... Analog Comparators CTMU Interface Resets (and delays) Instruction Set Packages Note 1: Peripherals are accessible through remappable pins. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY PIC24FJ32GA102 PIC24FJ64GA102 PIC24FJ32GA104 PIC24FJ64GA104 DC – 32 MHz 32K 64K 11,008 22,016 8,192 45 (41/4) Ports A and B 21 ...
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... Inst Register Divide Control Signals Support Reg Array Multiplier (2) MCLR 10-Bit (3) (3) RTCC Comparators ADC SPI UART I2C (3) (3) 1/2 1/2 1/2 Preliminary (1) PORTA 16 (9 I/O) PORTB (16 I/ (1) PORTC (10 I/ (1) RP RP0:RP25 16-Bit ALU 16 PMP/PSP CTMU © 2009 Microchip Technology Inc. ...
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... C3INA 26 23 C3INB 25 22 C3INC 2 27 C3IND 3 28 CLKI 9 6 CLKO 10 7 Legend: TTL = TTL input buffer ANA = Analog level input/output © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Input I/O Buffer QFN ANA A/D Analog Inputs ANA 21 I ANA 22 I ANA 23 I ...
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... ANA = Analog level input/output DS39951B-page 12 Input I/O Buffer QFN Interrupt-on-Change Inputs ANA CTMU External Edge Input ANA CTMU External Edge Input — Comparator Voltage Reference Output Voltage Regulator Disable Schmitt Trigger input buffer C™ C/SMBus input buffer Preliminary Description © 2009 Microchip Technology Inc. ...
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... PMD7 14 11 PMRD 24 21 PMWR 25 22 Legend: TTL = TTL input buffer ANA = Analog level input/output © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Input I/O Buffer QFN External Interrupt Input Master Clear (device Reset) Input. This line is brought low to cause a Reset. ...
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... ST 21 I/O ST PORTB Digital I/ I/O ST PORTC Digital I/ — Reference Clock Output Schmitt Trigger input buffer C™ C/SMBus input buffer Preliminary Description © 2009 Microchip Technology Inc. ...
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... SOSCO 12 9 T1CK 12 9 TCK 17 14 TDI 16 13 TDO 18 15 TMS 14 11 Legend: TTL = TTL input buffer ANA = Analog level input/output © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Input I/O Buffer QFN/ 21 I/O ST Remappable Peripheral (input or output I/O ...
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... Positive Supply for Microcontroller Core Logic (regulator disabled ANA A/D and Comparator Reference Voltage (low) Input ANA A/D and Comparator Reference Voltage (high) Input. P — Ground Reference for Logic and I/O Pins Schmitt Trigger input buffer C™ C/SMBus input buffer Preliminary Description © 2009 Microchip Technology Inc. ...
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... REF REF reference for analog modules is implemented Note: The AV and AV pins must always connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY FIGURE 2- MCLR (2) C6 ...
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... V IH Preliminary pin provides two specific device may be all that is required. The DD may be beneficial. A typical ) and fast signal transitions must IL EXAMPLE OF MCLR PIN CONNECTIONS R1 R2 MCLR PIC24FXXXX JP C1 and V specifications are met and V specifications are met. IL © 2009 Microchip Technology Inc. ...
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... Frequency (MHz) Note: Data for Murata GRM21BF50J106ZE01 shown. Measurements at 25° bias. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 2.5 ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming (ICSP) and debugging purposes recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible ...
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... Devices” application functionality. 2.8 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 kΩ kΩ resistor to V output to logic low. Preliminary on unused pins and drive the SS © 2009 Microchip Technology Inc. ...
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... Register Indirect modes. Each group offers up to seven addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY For most instructions, the core is capable of executing a data (or program data) memory read, a working reg- ister (data) read, a data memory write and a program (instruction) memory read per instruction cycle ...
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... Control Signals to Various Blocks DS39951B-page 22 Data Bus 16 16 Data Latch PCL Data RAM Address Loop Latch Control Logic RAGU WAGU EA MUX ROM Latch 16 Instruction Reg Hardware Multiplier Register Array Divide Support 16-Bit ALU Preliminary Peripheral Modules © 2009 Microchip Technology Inc. ...
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... W11 W12 W13 W14 W15 22 PUSH.S Registers or bits shaded for © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Description Working Register Array 23-Bit Program Counter ALU STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register Program Space Visibility Page Address Register ...
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... Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. DS39951B-page 24 U-0 U-0 — — (1) R-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1,2) Preliminary U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W-0 R/W bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 U-0 — ...
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... All multi-bit shift instructions only support Register Direct Addressing for both the operand source and result destination. A full summary of instructions that use the shift operation is provided below in Table 3-2. Description Preliminary © 2009 Microchip Technology Inc. ...
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... Device Config Registers Reserved DEVID (2) Note: Memory areas are not shown to scale. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY from either the 23-bit Program Counter (PC) during pro- gram execution, or from table operation or data space remapping, as described in Section 4.3 “Interfacing Program and Data Memory Spaces”. ...
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... TABLE 4-1: Device PIC24FJ32GB0 PIC24FJ64GB0 least significant word Instruction Width Preliminary FLASH CONFIGURATION WORDS FOR PIC24FJ64GA104 FAMILY DEVICES Program Configuration Memory Word (Words) Addresses 0057F8h: 11,008 0057FEh 00ABF8h: 22,016 00ABFEh PC Address (LSW Address) 0 000000h 000002h 000004h 000006h © 2009 Microchip Technology Inc. ...
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... FFFFh Note: Data memory areas are not shown to scale. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY PIC24FJ64GA104 family devices implement a total of 16 Kbytes of data memory. Should an EA point to a location outside of this area, an all zero word or byte will be returned. ...
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... CRC/Comp Comparators System/DS NVM/PMD — Preliminary xxA0 xxC0 xxE0 Interrupts — Compare — — I/O — — — — — — — — — PPS — — — — © 2009 Microchip Technology Inc. ...
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TABLE 4-3: CPU CORE REGISTERS MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 ...
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TABLE 4-4: ICN REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE (1) CNEN2 0062 — CN30IE CN29IE CN28IE CN27IE CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE (1) ...
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TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 INTCON1 0080 NSTDIS — — — INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 U2TXIF U2RXIF INT2IF ...
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TABLE 4-6: TIMER REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — ...
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TABLE 4-7: INPUT CAPTURE REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name IC1CON1 0140 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 IC1CON2 0142 — — — — IC1BUF 0144 IC1TMR 0146 IC2CON1 0148 — — ICSIDL ...
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TABLE 4-8: OUTPUT COMPARE REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 OC1CON1 0190 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 OC1CON2 0192 FLTMD FLTOUT FLTTRIEN OCINV OC1RS 0194 OC1R 0196 OC1TMR 0198 OC2CON1 019A ...
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TABLE 4-9: I C™ REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 I2C1RCV 0200 — — — — I2C1TRN 0202 — — — — I2C1BRG 0204 — — — — I2C1CON 0206 I2CEN — ...
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TABLE 4-11: SPI REGISTER MAPS File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 SPI1STAT 0240 SPIEN — SPISIDL — SPI1CON1 0242 — — — DISSCK SPI1CON2 0244 FRMEN SPIFSD SPIFPOL — SPI1BUF 0248 SPI2STAT 0260 SPIEN — ...
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TABLE 4-15: PAD CONFIGURATION REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 PADCFG1 02FC — — — — Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-16: ADC REGISTER ...
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TABLE 4-18: PARALLEL MASTER/SLAVE PORT REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 PMCON 0600 PMPEN — PSIDL ADRMUX1 ADRMUX0 PMMODE 0602 BUSY IRQM1 IRQM0 INCM1 PMADDR 0604 — CS1 — — PMDOUT1 PMDOUT2 0606 ...
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TABLE 4-21: COMPARATORS REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 CMSTAT 0650 CMIDL — — — CVRCON 0652 — — — — CM1CON 0654 CEN COE CPOL — CM2CON 065C CEN COE CPOL — ...
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TABLE 4-23: SYSTEM REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR — — OSCCON 0742 — COSC2 COSC1 COSC0 CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 OSCTUN 0748 — — — — ...
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... W15 (before CALL) 000000000 PC<22:16> <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 4.3 Interfacing Program and Data Memory Spaces The PIC24F architecture uses a 24-bit wide program space and a 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space ...
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... Bits 24 Bits Select 1 0 PSVPAG 8 Bits 23 Bits Preliminary <15> <14:1> <0> PC<22:1> 0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx (1) Data EA<14:0> xxx xxxx xxxx xxxx 0 EA 1/0 16 Bits Bits Byte Select © 2009 Microchip Technology Inc. ...
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... FIGURE 4-6: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P<23:16> data address. Note that D<15:8>, the ‘phantom’ byte, will always be ‘0’. ...
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... PSV Area 800000h Preliminary 1111’ or 0000h Data EA<14:0> 8000h ...while the lower 15 bits of the EA specify an exact address within the FFFFh PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address. © 2009 Microchip Technology Inc. ...
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... Using Table Instruction User/Configuration Space Select © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may write program memory data in blocks of 64 instruc- tions (192 bytes time and erase program memory in blocks of 512 instructions (1536 bytes time. Manual” ...
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... Flash in RTSP mode. During a programming or erase operation, the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the operation and the WR bit is automatically cleared when the operation is finished. Preliminary © 2009 Microchip Technology Inc. ...
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... Memory row program operation (ERASE = operation (ERASE = 1) Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. 3: Available in ICSP™ mode only. Refer to device programming specification. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY (1) U-0 U-0 — — ...
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... Initialize in-page EA[15:0] pointer ; Set base address of erase block ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted Preliminary © 2009 Microchip Technology Inc. ...
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... MOV #LOW_WORD_31, W2 MOV #HIGH_BYTE_31, W3 TBLWTL W2, [W0] TBLWTH W3, [W0] © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY // Address of row to write // Initialize PM Page Boundary SFR // Initialize lower word of address // Set base address of erase block // with dummy latch write // Initialize NVMCON // Block all interrupts with priority <7 ...
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... Initialize lower word of address // Write to address low word // Write to upper byte // Increment address ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; ; ; and wait for completed Preliminary © 2009 Microchip Technology Inc. ...
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... TBLWT instructions to write latches __builtin_tblwtl(offset, progDataL); __builtin_tblwth(offset, progDataH); asm(“DISI #5”); __builtin_write_NVM(); © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY instructions write the desired data into the write latches and specify the lower 16 bits of the program memory address to write to. To configure the NVMCON register for a word write, set the NVMOP bits (NVMCON< ...
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... PIC24FJ64GA104 FAMILY NOTES: DS39951B-page 54 Preliminary © 2009 Microchip Technology Inc. ...
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... Enable Voltage Regulator Trap Conflict Illegal Opcode Configuration Mismatch Uninitialized W Register © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. ...
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... U-0 U-0 R/CO-0, HS — — DPSLP R/W-0 R/W-0, R/W-0 (2) WDTO SLEEP HS = Hardware Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary R/W-0 R/W-0 CM PMSLP bit 8 R/W-1 R/W-1 IDLE BOR POR bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... FNOSC Configuration bits (CW2<10:8>) BOR MCLR COSC Control bits (OSCCON<14:12>) WDTO SWR © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY (1) (CONTINUED) Setting Event 6.2 Device Reset Times The Reset times for various types of device Reset are summarized in Table 6-3. Note that the System Reset signal, SYSRST, is released after the POR and PWRT delay times expire ...
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... PWRT OST RST PWRT RST PWRT RST PWRT RST PWRT RST PWRT FRC RST PWRT RST PWRT FRC T RST ). DD Preliminary © 2009 Microchip Technology Inc. Notes — FRC LPRC LOCK + LOCK OST + LOCK — FRC LPRC LOCK + LOCK OST + LOCK — ...
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... FRC Oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine (TSR). © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 6.3 Special Function Register Reset ...
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... PIC24FJ64GA104 FAMILY NOTES: DS39951B-page 60 Preliminary © 2009 Microchip Technology Inc. ...
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... PIC24FJ64GA104 family devices non-maskable traps and unique interrupts. These are summarized in Table 7-1 and Table 7-2. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 7-1. Access to the ...
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... Alternate Interrupt Vector Table (AIVT) 00017Ch 00017Eh 000180h 0001FEh 000200h AIVT Address 000104h Reserved 000106h Oscillator Failure 000108h Address Error 00010Ah Stack Error 00010Ch Math Error 00010Eh Reserved 000110h Reserved 000112h Reserved Preliminary (1) (1) Trap Source © 2009 Microchip Technology Inc. ...
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... SPI1 Event SPI2 Error SPI2 Event Timer1 Timer2 Timer3 Timer4 Timer5 UART1 Error UART1 Receiver UART1 Transmitter UART2 Error UART2 Receiver UART2 Transmitter © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Vector AIVT IVT Address Address 13 00002Eh 00012Eh 18 000038h 000138h 67 00009Ah 00019Ah ...
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... ISR is used for multiple vectors – such as when ISR remapping is used in boot- loader applications. It also could be used to check if another interrupt is pending while in an ISR. All interrupt registers are described in Register 7-1 through Register 7-32, on the following pages. Preliminary © 2009 Microchip Technology Inc. ...
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... See Register 3-2 for the description of the remaining bit(s) that are not dedicated to interrupt control functions. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 — ...
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... Unimplemented: Read as ‘0’ DS39951B-page 66 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 MATHERR ADDRERR STKERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 U-0 OSCFAIL — bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 U-0 — — ...
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... Interrupt request has not occurred DS39951B-page 68 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF U-0 R/W-0 R/W-0 — T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPF1IF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... MI2C1IF: Master I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 R/W-0 R/W-0 T5IF T4IF ...
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... Interrupt request has not occurred DS39951B-page 70 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. R/W-0 U-0 OC5IF — bit 8 R/W-0 R/W-0 SPI2IF SPF2IF bit Bit is unknown ...
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... Interrupt request has not occurred bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 U-0 — — — ...
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... Unimplemented: Read as ‘0’ DS39951B-page 72 U-0 U-0 U-0 — — — U-0 R/W-0 R/W-0 — CRCIF U2ERIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. U-0 R/W-0 — LVDIF bit 8 R/W-0 U-0 U1ERIF — bit Bit is unknown ...
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... IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE ...
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... DS39951B-page 74 R/W-0 R/W-0 (1) T5IE T4IE R/W-0 R/W-0 (1) INT1IE CNIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) Preliminary R/W-0 R/W-0 U-0 OC4IE OC3IE — bit 8 R/W-0 R/W-0 R/W-0 CMIE MI2C1IE SI2C1IE bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 U-0 — — — ...
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... Unimplemented: Read as ‘0’ DS39951B-page 76 U-0 U-0 U-0 — — — U-0 U-0 R/W-0 — — MI2C2IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 U-0 SI2C2IE — bit Bit is unknown ...
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... U2ERIE: UART2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 U-0 — — — U-0 ...
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... Interrupt source is disabled DS39951B-page 78 R/W-0 U-0 R/W-1 T1IP0 — OC1IP2 R/W-0 U-0 R/W-1 IC1IP0 — INT0IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC1IP1 OC1IP0 bit 8 R/W-0 R/W-0 INT0IP1 INT0IP0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 U-0 R/W-1 T2IP0 — OC2IP2 R/W-0 ...
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... Interrupt source is disabled DS39951B-page 80 R/W-0 U-0 R/W-1 U1RXIP0 — SPI1IP2 R/W-0 U-0 R/W-1 SPF1IP0 — T3IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1IP1 SPI1IP0 bit 8 R/W-0 R/W-0 T3IP1 T3IP0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 U-0 — — — R/W-0 ...
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... Interrupt source is disabled DS39951B-page 82 R/W-0 U-0 R/W-1 CNIP0 — CMIP2 R/W-0 U-0 R/W-1 MI2C1IP0 — SI2C1IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 CMIP1 CMIP0 bit 8 R/W-0 R/W-0 SI2C1IP1 SI2C1IP0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 85
... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 U-0 — — — U-0 ...
Page 86
... Unimplemented: Read as ‘0’ DS39951B-page 84 R/W-0 U-0 R/W-1 T4IP0 — OC4IP2 R/W-0 U-0 U-0 OC3IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC4IP1 OC4IP0 bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 87
... Unimplemented: Read as ‘0’ bit 2-0 T5IP<2:0>: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 U-0 R/W-1 U2TXIP0 — U2RXIP2 R/W-0 ...
Page 88
... Interrupt source is disabled DS39951B-page 86 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 SPI2IP0 — SPF2IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 SPF2IP1 SPF2IP0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 89
... IC3IP<2:0>: Input Capture Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 U-0 R/W-1 IC5IP0 — IC4IP2 R/W-0 ...
Page 90
... Unimplemented: Read as ‘0’ DS39951B-page 88 U-0 U-0 U-0 — — — R/W-0 U-0 U-0 OC5IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 91
... PMPIP<2:0>: Parallel Master Port Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 U-0 — — — R/W-0 ...
Page 92
... Unimplemented: Read as ‘0’ DS39951B-page 90 U-0 U-0 R/W-1 — — MI2C2IP2 R/W-0 U-0 U-0 SI2C2IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 MI2C2IP1 MI2C2IP0 bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 93
... RTCIP<2:0>: Real-Time Clock/Calendar Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 R/W-1 — — RTCIP2 U-0 ...
Page 94
... Unimplemented: Read as ‘0’ DS39951B-page 92 R/W-0 U-0 R/W-1 CRCIP0 — U2ERIP2 R/W-0 U-0 U-0 U1ERIP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 U2ERIP1 U2ERIP0 bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 95
... CTMUIP<2:0>: CTMU Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 U-0 — — — U-0 ...
Page 96
... Interrupt Vector pending is number 8 DS39951B-page 94 U-0 R-0 R-0 — ILR3 ILR2 R-0 R-0 R-0 VECNUM4 VECNUM3 VECNUM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R-0 R-0 ILR1 ILR0 bit 8 R-0 R-0 VECNUM1 VECNUM0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 97
... ISR will be re-entered immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, ...
Page 98
... PIC24FJ64GA104 FAMILY NOTES: DS39951B-page 96 Preliminary © 2009 Microchip Technology Inc. ...
Page 99
... Secondary Oscillator SOSCO SOSCEN Enable SOSCI Oscillator © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY • Software-controllable switching between various clock sources • Software-controllable postscaler for selective clocking of CPU for system power savings • A Fail-Safe Clock Monitor (FSCM) that detects ...
Page 100
... Primary 00 Primary 10 Primary 01 Primary 00 Internal 11 Internal 11 Preliminary the program memory (refer to Oscillator Configuration bits, (Configuration Word 2<1:0>), and Configuration bits (Configuration FNOSC2: Note FNOSC0 1, 2 111 1 110 1 101 1 100 011 011 010 010 010 1 001 1 000 © 2009 Microchip Technology Inc. ...
Page 101
... IOL1WAY Configuration bit is ‘1’ once the IOLOCK bit is set, it cannot be cleared. 3: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL clock mode is selected. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY The CLKDIV register (Register 8-2) controls the features associated with Doze mode, as well as the postscaler for the FRC Oscillator ...
Page 102
... The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is ‘1’ once the IOLOCK bit is set, it cannot be cleared. 3: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL clock mode is selected. DS39951B-page 100 (2) (3) Preliminary © 2009 Microchip Technology Inc. ...
Page 103
... MHz (divide by 4) 001 = 4 MHz (divide by 2) 000 = 8 MHz (divide by 1) bit 7-0 Unimplemented: Read as ‘0’ Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 R/W-0 R/W-0 (1) DOZE0 ...
Page 104
... Configuration bits. The OSWEN control bit (OSCCON<0>) has no effect when clock switching is disabled held at ‘0’ at all times. Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 R/W-0 (1) (1) (1) TUN2 TUN1 TUN0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 105
... In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY A recommended code sequence for a clock switch includes the following: 1. Disable interrupts during the OSCCON register unlock and write sequence ...
Page 106
... Sleep mode. Clearing the ROSEL bit allows the reference output frequency to change as the system clock changes during any clock switches. Preliminary ® ® and PICmicro Devices” ® Oscillator Design” /2) available in OSC © 2009 Microchip Technology Inc. ...
Page 107
... Base clock value divided by 16 0011 = Base clock value divided by 8 0010 = Base clock value divided by 4 0001 = Base clock value divided by 2 0000 = Base clock value bit 7-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 R/W-0 R/W-0 ROSEL RODIV3 ...
Page 108
... PIC24FJ64GA104 FAMILY NOTES: DS39951B-page 106 Preliminary © 2009 Microchip Technology Inc. ...
Page 109
... Put the device into IDLE mode BSET DSCON, #DSEN ; Enable Deep Sleep PWRSAV #SLEEP_MODE ; Put the device into Deep SLEEP mode © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY The assembly syntax of the PWRSAV instruction is shown in Example 9-1. Note: SLEEP_MODE constants defined in the assembler include file for the selected device. Manual” ...
Page 110
... Enable Deep Sleep mode by setting the DSEN bit (DSCON<15>). 6. Enter Deep Sleep mode by immediately issuing a PWRSAV #0 instruction. Any time the DSEN bit is set, all bits in the DSWAKE register will be automatically cleared. Preliminary © 2009 Microchip Technology Inc. CY Sleep WDT” for ...
Page 111
... PWRSAV instruction, in the event that the PWRSAV instruction is skipped and the device does not enter Deep Sleep mode. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Examples for implementing these cases are shown in Example 9- recommended that an assembler, or in-line C routine be used in these cases, to ensure that the code executes in the number of cycles required ...
Page 112
... Deep Sleep remain as output pins during Deep Sleep. While in this mode, they continue to drive the output level determined by their corresponding LAT bit at the time of entry into Deep Sleep. Preliminary © 2009 Microchip Technology Inc. may drop depending CAP has dropped CAP . ...
Page 113
... For more details on the CW4 Configuration register and DSWDT configuration options, refer to Section 25.0 “Special Features”. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 9.2.4.8 Switching Clocks in Deep Sleep Mode Both the RTCC and the DSWDT may run from either SOSC or the LPRC clock source ...
Page 114
... The DSEN bit is automatically cleared. 11. Read and clear the DPSLP status bit in RCON, and the DSWAKE status bits. 12. Read the DSGPRx registers (optional). 13. Once all state related configurations are complete, clear the RELEASE bit. 14. Application resumes normal operation. Preliminary © 2009 Microchip Technology Inc. ...
Page 115
... These bits are reset only in the case of a POR event outside of Deep Sleep mode. 2: Reset value is ‘0’ for initial power-on POR only and ‘1’ for Deep Sleep POR. 3: This is a status bit only; a DSBOR event will NOT cause a wake-up from Deep Sleep. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 U-0 — ...
Page 116
... R/W-0, HS R/W-0, HS R/W-0, HS (1) (1) DSWDT DSRTC DSMCLR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) (1) (1) (2) Preliminary U-0 R/W-0, HS (1) — DSINT0 bit 8 U-0 R/W-0, HS (1) (2) — DSPOR bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 117
... Enabling the automatic return to full-speed CPU operation on interrupts is enabled by setting the ROI bit (CLKDIV<15>). By default, interrupt events have no effect on Doze mode operation. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 9.4 Selective Peripheral Module Control Idle and Doze modes allow users to substantially reduce power consumption by slowing or stopping the CPU clock ...
Page 118
... PIC24FJ64GA104 FAMILY NOTES: DS39951B-page 116 Preliminary © 2009 Microchip Technology Inc. ...
Page 119
... CK WR PORT Data Latch Read LAT Read PORT © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled ...
Page 120
... INPUT VOLTAGE TOLERANCE Tolerated Port or Pin Input PORTA<4:0> PORTB<15:12> PORTB<4:0> (1) PORTC<3:0> (1) PORTA<10:7> 5.5V PORTB<11:7> PORTB<6:5> (1) PORTC<9:4> Note 1: Not available on 28-pin devices. Preliminary © 2009 Microchip Technology Inc. on these pins DD Description Only V input levels DD tolerated. Tolerates input levels above V , useful for DD most standard logic. ...
Page 121
... Select is performed in software and generally does not require the device to be reprogrammed. Hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping once it has been established. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 10.4.1 AVAILABLE PINS The Peripheral Pin Select feature is used with a range pins, depending on the particular device and its pin count ...
Page 122
... RPINR4 U1CTS RPINR18 U1RX RPINR18 U2CTS RPINR19 U2RX RPINR19 Preliminary (1) Function Mapping Bits INT1R<5:0> INT2R<5:0> IC1R<5:0> IC2R<5:0> IC3R<5:0> IC4R<5:0> IC5R<5:0> OCFAR<5:0> OCFBR<5:0> SCK1R<5:0> SDI1R<5:0> SS1R<5:0> SCK2R<5:0> SDI2R<5:0> SS2R<5:0> T2CKR<5:0> T3CKR<5:0> T4CKR<5:0> T5CKR<5:0> U1CTSR<5:0> U1RXR<5:0> U2CTSR<5:0> U2RXR<5:0> © 2009 Microchip Technology Inc. ...
Page 123
... The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function. ® 3: IrDA BCLK functionality uses this output. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY the bit field corresponds to one of the peripherals and that peripheral’s output is mapped to the pin (see Table 10-3). ...
Page 124
... Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Programming IOL1WAY allows users unlimited access (with the proper use of the unlock sequence) to the Peripheral Pin Select registers. Preliminary © 2009 Microchip Technology Inc. ...
Page 125
... To be safe, fixed digital peripherals that share the same pin should be disabled when not in use. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Along these lines, configuring a remappable pin for a specific peripheral does not automatically turn that feature on ...
Page 126
... INT2R3 INT2R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 INT1R1 INT1R0 bit 8 U-0 U-0 — — bit Bit is unknown U-0 U-0 — — bit 8 R/W-1 R/W-1 INT2R1 INT2R0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 127
... T5CKR<4:0>: Assign Timer5 External Clock (T5CK) to Corresponding RPn or RPIn Pin bits bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 T4CKR<4:0>: Assign Timer4 External Clock (T4CK) to Corresponding RPn or RPIn Pin bits © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-1 R/W-1 R/W-1 T3CKR4 ...
Page 128
... IC3R3 IC3R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 IC2R1 IC2R0 bit 8 R/W-1 R/W-1 IC1R1 IC1R0 bit Bit is unknown R/W-1 R/W-1 IC4R1 IC4R0 bit 8 R/W-1 R/W-1 IC3R1 IC3R0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 129
... OCFBR<4:0>: Assign Output Compare Fault B (OCFB) to Corresponding RPn or RPIn Pin bits bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 OCFAR<4:0>: Assign Output Compare Fault A (OCFA) to Corresponding RPn or RPIn Pin bits © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 U-0 — ...
Page 130
... U2RXR3 U2RXR2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 U1CTSR1 U1CTSR0 bit 8 R/W-1 R/W-1 U1RXR1 U1RXR0 bit Bit is unknown R/W-1 R/W-1 U2CTSR1 U2CTSR0 bit 8 R/W-1 R/W-1 U2RXR1 U2RXR0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 131
... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 SS1R<4:0>: Assign SPI1 Slave Select Input (SS1IN) to Corresponding RPn or RPIn Pin bits © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-1 R/W-1 R/W-1 SCK1R4 SCK1R3 SCK1R2 ...
Page 132
... SS2R3 SS2R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 SCK2R1 SCK2R0 bit 8 R/W-1 R/W-1 SDI2R1 SDI2R0 bit Bit is unknown U-0 U-0 — — bit 8 R/W-1 R/W-1 SS2R1 SS2R0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 133
... Peripheral output number n is assigned to pin, RP3 (see Table 10-3 for peripheral function numbers). bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP2R<4:0>: RP2 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP2 (see Table 10-3 for peripheral function numbers). © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 R/W-0 R/W-0 RP1R4 ...
Page 134
... RP6R3 RP6R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 RP5R1 RP5R0 bit 8 R/W-0 R/W-0 RP4R1 RP4R0 bit Bit is unknown R/W-0 R/W-0 RP7R1 RP7R0 bit 8 R/W-0 R/W-0 RP6R1 RP6R0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 135
... Peripheral output number n is assigned to pin, RP11 (see Table 10-3 for peripheral function numbers). bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP10R<4:0>: RP10 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP10 (see Table 10-3 for peripheral function numbers). © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 R/W-0 R/W-0 RP9R4 ...
Page 136
... RP14R3 RP14R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 RP13R1 RP13R0 bit 8 R/W-0 R/W-0 RP12R1 RP12R0 bit Bit is unknown R/W-0 R/W-0 RP15R1 RP15R0 bit 8 R/W-0 R/W-0 RP14R1 RP14R0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 137
... RP18R<4:0>: RP18 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP18 (see Table 10-3 for peripheral function numbers). Note 1: This register is unimplemented in 28-pin devices; all bits read as ‘0’. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 R/W-0 R/W-0 ...
Page 138
... RP22R3 RP22R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary (1) R/W-0 R/W-0 RP21R1 RP21R0 bit 8 R/W-0 R/W-0 RP20R1 RP20R0 bit Bit is unknown (1) R/W-0 R/W-0 RP23R1 RP23R0 bit 8 R/W-0 R/W-0 RP22R1 RP22R0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 139
... RP24R<5:0>: RP24 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP24 (see Table 10-3 for peripheral function numbers). Note 1: This register is unimplemented in 28-pin devices; all bits read as ‘0’. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 R/W-0 R/W-0 ...
Page 140
... PIC24FJ64GA104 FAMILY NOTES: DS39951B-page 138 Preliminary © 2009 Microchip Technology Inc. ...
Page 141
... SOSCO/ T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Figure 11-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1). 2. Select the timer prescaler ratio using the TCKPS<1:0> bits. ...
Page 142
... DS39951B-page 140 (1) U-0 U-0 — — R/W-0 U-0 R/W-0 TCKPS0 — TSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /2) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 U-0 TCS — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 143
... Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. Set the T32 bit (T2CON<3> or T4CON<3> = 1). ...
Page 144
... The ADC event trigger is available only on Timer 2/3 in 32-bit mode and Timer 3 in 16-bit mode. DS39951B-page 142 1x Gate Sync PR3 PR2 (PR5) (PR4) Comparator LSB TMR2 TMR3 (TMR4) (TMR5 TMR3HLD (TMR5HLD) Preliminary TCKPS<1:0> 2 TON Prescaler 1, 8, 64, 256 (2) TGATE (2) TCS Sync © 2009 Microchip Technology Inc. ...
Page 145
... Note 1: The timer clock input must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral Pin Select (PPS)” for more information. 2: The ADC event trigger is available only on Timer3. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 1x Gate Sync ...
Page 146
... DS39951B-page 144 U-0 U-0 — — R/W-0 R/W-0 (1) TCKPS0 T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) /2) Preliminary (3) U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 (2) — TCS — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 147
... If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select (PPS)” for more information. 3: Changing the value of TyCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 (1) — ...
Page 148
... PIC24FJ64GA104 FAMILY NOTES: DS39951B-page 146 Preliminary © 2009 Microchip Technology Inc. ...
Page 149
... Reset Trigger and Sync Sources Note 1: The ICx inputs must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral Pin Select (PPS)” for more information. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 13.1 General Operating Modes 13.1.1 ...
Page 150
... ICyBUF for the msw). At least one capture value is available in the FIFO buffer when the odd module’s ICBNE bit (ICxCON1<3>) becomes set. Continue to read the buffer registers until ICBNE is cleared (perform automatically by hardware). Preliminary © 2009 Microchip Technology Inc. for both modules configure Trigger ...
Page 151
... Input capture module turned off Note 1: The ICx input must also be configured to an available RPn pin. For more information, see Section 10.4 “Peripheral Pin Select (PPS)”. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 R/W-0 ICTSEL2 ...
Page 152
... DS39951B-page 150 U-0 U-0 — — R/W-0 R/W-1 SYNCSEL4 SYNCSEL3 SYNCSEL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) Preliminary U-0 U-0 R/W-0 — — IC32 bit 8 R/W-1 R/W-0 R/W-1 SYNCSEL1 SYNCSEL0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 153
... Compare or PWM events are generated each time a match between the internal counter and one of the Period registers occurs. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY In Synchronous mode, the module begins performing its compare or PWM operation as soon as its selected clock source is enabled. Whenever an event occurs on the selected sync source, the module’ ...
Page 154
... Pin Select (PPS)” for more information. DS39951B-page 152 OCxCON1 OCxCON2 OCxR Match Event Comparator OCxTMR Reset Match Event Comparator OCxRS Preliminary DCBx OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLTx OCFLTx (1) OCx Pin OC Output and Fault Logic OCFA/ OCFB/ CxOUT OCx Interrupt © 2009 Microchip Technology Inc. ...
Page 155
... Trigger mode operation starts after a trigger source event occurs. 8. Set the OCM<2:0> bits for the appropriate compare operation (= 0xx). © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY For 32-bit cascaded operation, these steps are also necessary: 1. Set ...
Page 156
... Match Event OCxTMR Rollover Reset Comparator Match Event OCxRS Buffer Rollover/Reset OCxRS Preliminary a clock source by writing the DCBx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLTx OCFLTx OCx Pin OC Output and (1) Fault Logic OCFA/ OCFB/ CxOUT OCx Interrupt © 2009 Microchip Technology Inc. ...
Page 157
... Note 1: Based Doze mode and PLL are disabled. CY OSC © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 14.3.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the OCxRS and OCxR registers. The OCxRS and OCxR registers can be written to at any time, but the duty cycle value is not latched until a match between PRy and TMRy occurs (i ...
Page 158
... Hz 122 Hz 977 FFFFh 7FFFh 0FFFh 244 Hz 488 Hz 3.9 kHz FFFFh 7FFFh 0FFFh Preliminary ( MHz) CY 3.9 kHz 31.3 kHz 125 kHz 03FFh 007Fh 001Fh ( MHz) CY 15.6 kHz 125 kHz 500 kHz 03FFh 007Fh 001Fh © 2009 Microchip Technology Inc. ...
Page 159
... The OCx output must also be configured to an available RPn pin. For more information, see Section 10.4 “Peripheral Pin Select (PPS)”. 2: The comparator module used for Fault input varies with the OCx module. OC1 and OC2 use Comparator 1; OC3 and OC4 use Comparator 2; OC5 uses Comparator 3. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 R/W-0 R/W-0 ...
Page 160
... The OCx output must also be configured to an available RPn pin. For more information, see Section 10.4 “Peripheral Pin Select (PPS)”. 2: The comparator module used for Fault input varies with the OCx module. OC1 and OC2 use Comparator 1; OC3 and OC4 use Comparator 2; OC5 uses Comparator 3. DS39951B-page 158 (1) Preliminary © 2009 Microchip Technology Inc. ...
Page 161
... SYNCSEL setting. 2: Use these inputs as trigger sources only and never as sync sources. 3: These bits affect the rising edge when OCINV = 1. The bits have no effect when the OCM bits (OCxCON1<1:0>) = 001. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 U-0 R/W-0 (3) OCINV DCB1 — ...
Page 162
... Use these inputs as trigger sources only and never as sync sources. 3: These bits affect the rising edge when OCINV = 1. The bits have no effect when the OCM bits (OCxCON1<1:0>) = 001. DS39951B-page 160 (1) (2) (2) (2) (2) (2) (2) (2) (2) (1) (1) (1) (1) (1) Preliminary © 2009 Microchip Technology Inc. ...
Page 163
... Enhanced Buffer mode. The module also supports a basic framed SPI protocol while operating in either Master or Slave mode. A total of four framed SPI configurations are supported. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY The SPI serial interface consists of four pins: • SDIx: Serial Data Input • ...
Page 164
... Clear the SPIROV bit (SPIxSTAT<6>). 7. Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>). 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer Write SPIxBUF 16 Internal Data Bus Preliminary registers with MSTEN 1:1/4/16/64 Primary F CY Prescaler SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock © 2009 Microchip Technology Inc. ...
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... SDOx bit 0 SDIx SPIxSR Transfer 8-Level FIFO Receive Buffer SPIxBUF Read SPIxBUF © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. Clear the SPIxBUF register using interrupts: a) Clear the SPIxIF bit in the respective IFS register ...
Page 166
... U-0 — — SPIBEC2 R/W-0 R/W-0 SISEL2 SISEL1 HS = Hardware Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R-0 R-0 R-0 SPIBEC1 SPIBEC0 bit 8 R/W-0 R-0 R-0 SISEL0 SPITBF SPIRBF bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR. Note 1: If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 10.4 “Peripheral Pin Select (PPS)” for more information. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Preliminary DS39951B-page 165 ...
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... R/W-0 R/W-0 (1) (2) DISSCK DISSDO MODE16 R/W-0 R/W-0 R/W-0 SPRE2 SPRE1 SPRE0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (3) (4) Preliminary R/W-0 R/W-0 (3) SMP CKE bit 8 R/W-0 R/W-0 PPRE1 PPRE0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced buffer enabled 0 = Enhanced buffer disabled (Legacy mode) © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 U-0 — — ...
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... SDIx SDOx Serial Clock SCKx SCKx (1) SSx SSx SSEN (SPIxCON1<7> MSTEN (SPIxCON1<5> and SPIBEN (SPIxCON2<0> Preliminary (SPIxRXB) Shift Register (SPIxSR) LSb (SPIxTXB) SPIx Buffer (2) (SPIxBUF) Shift Register (SPIxSR) MSb LSb 8-Level FIFO Buffer SPIx Buffer (2) (SPIxBUF) © 2009 Microchip Technology Inc. ...
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... FIGURE 15-7: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM PIC24F (SPI Slave, Frame Master) FIGURE 15-8: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM PIC24F (SPI Slave, Frame Slave) © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY PROCESSOR 2 SDOx SDIx SDIx SDOx Serial Clock SCKx ...
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... Preliminary (1) 4:1 6:1 8:1 4000 2667 2000 1000 667 500 250 167 125 1250 833 625 313 208 156 © 2009 Microchip Technology Inc. ...
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... Bus Repeater mode, allowing the acceptance of all messages as a slave regardless of the address • Automatic SCL A block diagram of the module is shown in Figure 16-1. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 16.1 Communicating as a Master in a Single Master Environment The details of sending a message in Master mode depends on the communications protocol for the device being communicated with ...
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... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSB Reload Control Preliminary Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2009 Microchip Technology Inc. ...
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... The address bits listed here will never cause an address match, independent of address mask settings. 2: The address will be Acknowledged only if GCEN = match on this address can only occur on the upper byte in 10-Bit Addressing mode. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 16.3 Slave Address Masking The I2CxMSK register (Register 16-3) designates address bit positions as “ ...
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... R/W-0, HC R/W-0, HC ACKEN RCEN PEN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C pins are controlled by port functions Slave slave slave) Preliminary R/W-0 R/W-0 DISSLW SMEN bit 8 R/W-0, HC R/W-0, HC RSEN SEN bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Repeated Start condition not in progress bit 0 SEN: Start Condition Enabled bit (when operating Initiates Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence Start condition not in progress © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 2 C master. Applicable during master receive.) 2 ...
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... HS = Hardware Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C slave) Preliminary R-0, HSC R-0, HSC GCSTAT ADD10 bit 8 R-0, HSC R-0, HSC RBF TBF bit 0 HSC = Hardware Settable/Clearable bit x = Bit is unknown 2 C module is busy © 2009 Microchip Technology Inc. ...
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... Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 2 C slave device address byte. ...
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... DS39951B-page 178 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 AMSK4 AMSK3 AMSK2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 AMSK9 AMSK8 bit 8 R/W-0 R/W-0 AMSK1 AMSK0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Note: The UART inputs and outputs must all be assigned to available RPn pins before use. Please see Section 10.4 “Peripheral Pin Select (PPS)” for more information. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY • Fully Integrated Baud Rate Generator with 16-Bit Prescaler • ...
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... Preliminary /(16 * 65536). UART BAUD RATE WITH (1,2) BRGH = • (UxBRG + – • Baud Rate denotes the instruction cycle clock = F /2, Doze mode CY OSC /4 CY (1) © 2009 Microchip Technology Inc. ...
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... Write ‘55h’ to UxTXREG; this loads the Sync character into the transmit FIFO. 5. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 17.5 Receiving in 8-Bit or 9-Bit Data Mode 1. ...
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... DS39951B-page 182 R/W-0 R/W-0 U-0 (2) IREN RTSMD — R/W-0 R/W-0 R/W-0 RXINV BRGH PDSEL1 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary R/W-0 R/W-0 UEN1 UEN0 bit 8 R/W-0 R/W-0 PDSEL0 STSEL bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select (PPS)” for more information. 2: This feature is only available for the 16x BRG mode (BRGH = 0). © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Preliminary DS39951B-page 183 ...
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... R/W-0 — UTXBRK UTXEN R-1 R-0 R-0 RIDLE PERR FERR HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary R-0 R-1 (2) UTXBF TRMT bit 8 R/C-0 R-0 OERR URXDA bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1 UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select (PPS)” for more information. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Preliminary DS39951B-page 185 ...
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... PIC24FJ64GA104 FAMILY NOTES: DS39951B-page 186 Preliminary © 2009 Microchip Technology Inc. ...
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... PMP MODULE OVERVIEW PIC24F Parallel Master Port (1) Note 1: PMA<10:2> bits are not available on 28-pin devices. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Key features of the PMP module include: • Programmable Address Lines • One Chip Select Line • Programmable Strobe Options: - Individual Read and Write Strobes or ...
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... R/W-0 (1) (1) ADRMUX1 ADRMUX0 PTBEEN (2) (2) U-0 R/W-0 — CS1P U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (2) Preliminary R/W-0 R/W-0 R/W-0 PTWREN PTRDEN bit 8 R/W-0 R/W-0 R/W-0 BEP WRSP RDSP bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... For Master Mode 1 (PMMODE<9:8> Read/write strobe active-high (PMRD/PMWR Read/write strobe active-low (PMRD/PMWR) Note 1: PMA<10:2> bits are not available on 28-pin devices. 2: These bits have no effect when their corresponding pins are used as address lines. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Preliminary DS39951B-page 189 ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ; multiplexed address phase multiplexed address phase multiplexed address phase multiplexed address phase Preliminary R/W-0 R/W-0 MODE1 MODE0 bit 8 R/W-0 R/W-0 (1) (1) WAITE1 WAITE0 bit Bit is unknown (1) ) (1) © 2009 Microchip Technology Inc. ...
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... PTEN<1:0>: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL 0 = PMA1 and PMA0 pads function as port I/O Note 1: PMA<10:2> bits are not available on 28-pin devices. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 — — ...
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... DS39951B-page 192 U-0 R-0 R-0 — IB3F IB2F U-0 R-1 R-1 — OB3E OB2E U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. R-0 R-0 IB1F IB0F bit 8 R-1 R-1 OB1E OB0E bit Bit is unknown ...
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... PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffers Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL<10>) bit needs to be set. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 U-0 — ...
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... PMDOUT2H (3) PMWR PMDOUT1<7:0> (0) PMDOUT2<7:0> (2) PMA<10:0> PMD<7:0> PMCS1 PMRD PMWR Preliminary Address Bus Data Bus Control Lines Read Address Decode PMDIN1L (0) PMDIN1H (1) PMDIN2L (2) PMDIN2H (3) Input Register (Buffer) PMDIN1<7:0> (0) PMDIN1<15:8> (1) PMDIN2<7:0> (2) PMDIN2<15:8> (3) Address Bus Data Bus Control Lines © 2009 Microchip Technology Inc. ...
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... PMD<7:0> PMALL PMALH PMCS1 PMRD PMWR FIGURE 18-8: EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION PIC24F PMD<7:0> PMALL PMA<10:8> PMCS1 PMRD PMWR © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY PMA<10:8> PMD<7:0> PMA<7:0> PMCS1 PMALL PMRD PMWR PMD<7:0> PMA<7:0> PMA<15:8> PMCS1 PMALL PMALH ...
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... Parallel EEPROM A<n:0> D<7:0> Parallel EEPROM A<n:1> D<7:0> LCD Controller D<7:0> RS R/W E Preliminary Address Bus Data Bus Control Lines Address Bus Data Bus Control Lines Address Bus Data Bus Control Lines Address Bus Data Bus Control Lines © 2009 Microchip Technology Inc. ...
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... Alarm Event Comparator Alarm Registers with Masks Repeat Counter © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY • Alarm-configurable for half a second, one second, 10 seconds, one minute, 10 minutes, one hour, one day, one week, one month or one year • Alarm repeat with decrementing counter • ...
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... LPRC is used as the reference clock. //set the RTCWREN bit Preliminary ALRMVAL REGISTER MAPPING Alarm Value Register Window ALRMVAL<15:8> ALRMVAL<7:0> ALRMMIN ALRMSEC ALRMWD ALRMHR ALRMMNTH ALRMDAY — — © 2009 Microchip Technology Inc. ...