PIC16C63A-04E/SO Microchip Technology, PIC16C63A-04E/SO Datasheet - Page 2

• Manufacturer Part Number: PIC16C63A-04E/SO
• Description: IC MCU OTP 4KX14 PWM 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C63A-04E/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

PIC16C63A/65B/73B/74B
Clarifications/Corrections to the Data
Sheet:
In the Device Data Sheet (DS30605C), the following
clarifications and corrections should be noted:
1. Module: SSP (SPI™ Mode)
FIGURE 10-1:
DS80048C-page 2
RC3/SCK/SCL
RC4/SDI/SDA
RA5/SS/AN4
RC5/SDO
In Section 10.2 (“SPI Mode”), Figure 10-1 and the
note box immediately following it have been
amended to better demonstrate the peripheral OE
line of the SSP module and describe its
relationship to the TRISC<5> bit of PORTC.
Changes are indicated in bold.
Peripheral OE
Read
SS Control
TRISC<3>
Select
SMP:CKE
Edge
bit0
Enable
Select
Edge
SSP BLOCK DIAGRAM
(SPI MODE)
2
SSPBUF reg
SSPSR reg
SSPM3:SSPM0
Clock Select
4
2
TMR2 Output
Write
Prescaler
4, 16, 64
Clock
Shift
Data Bus
Internal
2
T
CY
Note 1: When the SPI module is in Slave mode
2: If the SPI is used in Slave mode with
3: When the SPI is in Slave mode with SS pin
with
(SSPCON<3:0> = 0100), the SPI module
will reset if the SS pin is set to V
CKE = 1, then SS pin control must be
enabled.
control enabled (SSPCON<3:0> = 0100),
the state of the SS pin can affect the state
read back from the TRISC<5> bit. The
peripheral OE signal from the SSP module
into PORTC controls the state that is read
back
Section 5.3 for information on PORTC). If
read-modify-write instructions, such as
BSF, are performed on the TRISC register
while the SS pin is high, this will cause the
TRISC<5> bit to be set, thus disabling the
SDO output.
from
SS
 2003 Microchip Technology Inc.
the
pin
TRISC<5>
control
DD
bit
enabled
.
(see