PIC18LF4450-I/P Microchip Technology, PIC18LF4450-I/P Datasheet - Page 22

• Manufacturer Part Number: PIC18LF4450-I/P
• Description: IC PIC MCU FLASH 8KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF4450-I/P

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC18
• No. Of I/o's: 34
• Ram Memory Size: 768Byte
• Cpu Speed: 48MHz
• No. Of Timers: 3
• No. Of Pwm: RoHS Compliant
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: RS- 232, USART, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM163025, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F2XXX/4XXX FAMILY
3.4
The ID locations are programmed much like the code
memory. The ID registers are mapped in addresses,
200000h through 200007h. These locations read out
normally even after code protection.
TABLE 3-8:
DS39622L-page 22
Step 1: Direct access to code memory and enable writes.
Step 2: Load write buffer with 8 bytes and write.
Note:
Command
0000
0000
0000
0000
0000
0000
0000
0000
1101
1101
1101
1111
0000
4-Bit
ID Location Programming
The user only needs to fill the first 8 bytes
of the write buffer in order to write the ID
locations.
8E A6
9C A6
0E 20
6E F8
0E 00
6E F7
0E 00
6E F6
<MSB><LSB>
<MSB><LSB>
<MSB><LSB>
<MSB><LSB>
00 00
WRITE ID SEQUENCE
Data Payload
BSF
BCF
MOVLW 20h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 00h
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2.
Write 2 bytes and post-increment address by 2.
Write 2 bytes and post-increment address by 2.
Write 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
EECON1, EEPGD
EECON1, CFGS
Table 3-8
write the ID locations.
In order to modify the ID locations, refer to the method-
ology described in
Memory”. As with code memory, the ID locations must
be erased before being modified.
Core Instruction
demonstrates the code sequence required to
Section 3.2.1 “Modifying Code
 2010 Microchip Technology Inc.