AT32UC3B064-Z2UT Atmel, AT32UC3B064-Z2UT Datasheet - Page 64

• Manufacturer Part Number: AT32UC3B064-Z2UT
• Description: IC MCU AVR32 64KB FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B064-Z2UT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFN
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP64-2 - STK600 SOCKET/ADAPTER FOR 64-TQFATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

32059K–03/2011
- SSC
4. Increased Power Consunption in VDDIO in sleep modes
1. Additional delay on TD output
2. TF output is not correct
3. Frame Synchro and Frame Synchro Data are delayed by one clock cycle
will not be turned off. This will result in a significantly higher power consumption during the
sleep mode.
Fix/Workaround
Before going to sleep modes where the system RC oscillator is stopped, make sure that the
factor between the CPU/HSB and PBx frequencies is less than or equal to 4.
If the OSC0 is enabled in crystal mode when entering a sleep mode where the OSC0 is dis-
abled, this will lead to an increased power consumption in VDDIO.
Fix/Workaround
Disable the OSC0 through the Power Manager (PM) before going to any sleep mode where
the OSC0 is disabled, or pull down or up XIN0 and XOUT0 with 1Mohm resistor.
A delay from 2 to 3 system clock cycles is added to TD output when:
TCMR.START = Receive Start,
TCMR.STTDLY = more than ZERO,
RCMR.START = Start on falling edge / Start on Rising edge / Start on any edge,
RFMR.FSOS = None (input).
Fix/Workaround
None.
TF output is not correct (at least emitted one serial clock cycle later than expected) when:
TFMR.FSOS = Driven Low during data transfer/ Driven High during data transfer
TCMR.START = Receive start
RFMR.FSOS = None (Input)
RCMR.START = any on RF (edge/level)
Fix/Workaround
None.
The frame synchro and the frame synchro data are delayed from 1 SSC_CLOCK when:
- Clock is CKDIV
- The START is selected on either a frame synchro edge or a level
- Frame synchro data is enabled
- Transmit clock is gated on output (through CKO field)
Fix/Workaround
Transmit or receive CLOCK must not be gated (by the mean of CKO field) when START
condition is performed on a generated frame synchro.
AT32UC3B
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