PIC16LC923-04I/PT Microchip Technology, PIC16LC923-04I/PT Datasheet - Page 157

• Manufacturer Part Number: PIC16LC923-04I/PT
• Description: IC MCU OTP 4KX14 LCD DVR 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC923-04I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 176 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

FIGURE 17-13:I
TABLE 17-11:I
Parameter
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
1997 Microchip Technology Inc.
D102*
*
100*
101*
102*
103*
106*
107*
109*
110*
No.
90*
91*
92*
Refer to Figure 17-2 for load conditions.
Characterized but not tested.
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
SDA
Out
SDA
In
SCL
T
T
T
T
T
T
T
HD
HD
SU
SU
SU
T
Sym
T
HIGH
LOW
T
Cb
T
BUF
AA
:
:
:
:
:
R
2
F
STO
STA
STA
DAT
DAT
C BUS DATA REQUIREMENTS
2
C BUS DATA TIMING
Characteristic
Clock high time
Clock low time
SDA and SCL rise
time
SDA and SCL fall time 100 kHz mode
START condition
setup time
START condition hold
time
Data input hold time
Data input setup time
STOP condition setup
time
Output valid from
clock
Bus free time
Bus capacitive loading
90
103
91
109
100 kHz mode
SSP Module
100 kHz mode
SSP Module
100 kHz mode
100 kHz mode
100 kHz mode
100 kHz mode
100 kHz mode
100 kHz mode
100 kHz mode
100 kHz mode
100
106
101
109
1.5T
1.5T
Min
250
4.0
4.7
4.7
4.0
4.7
4.7
—
—
—
—
0
107
CY
CY
1000
3500
Max
300
400
—
—
—
—
—
—
—
—
—
—
Units
pF
ns
ns
ns
ns
ns
s
s
s
s
s
s
PIC16C9XX
92
Device must operate at a mini-
mum of 1.5 MHz
Device must operate at a mini-
mum of 1.5 MHz
Only relevant for repeated
START condition
After this period the first clock
pulse is generated
Note 1
Time the bus must be free
before a new transmission can
start
102
DS30444E - page 157
110
Conditions