PIC24FJ256GB106T-I/PT Microchip Technology, PIC24FJ256GB106T-I/PT Datasheet - Page 13

IC PIC MCU FLASH 256K 64-TQFP

PIC24FJ256GB106T-I/PT

Manufacturer Part Number
PIC24FJ256GB106T-I/PT
Description
IC PIC MCU FLASH 256K 64-TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Fr

Specifications of PIC24FJ256GB106T-I/PT

Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
51
Program Memory Size
256KB (85.5K x 24)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUMA240014 - MODULE PLUG-IN PIC24
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC24FJ256GB106T-I/PTTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24FJ256GB106T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
3.2.2
The REGOUT control code allows for data to be
extracted from the device in ICSP mode. It is used to
clock the contents of the VISI register, out of the device,
over the PGDx pin. After the REGOUT control code is
received, the CPU is held Idle for 8 cycles. After these
8 cycles, an additional 16 cycles are required to clock the
data out (see Figure 3-3).
The REGOUT code is unique because the PGDx pin is
an input when the control code is transmitted to the
device. However, after the control code is processed,
the PGDx pin becomes an output as the VISI register is
shifted out.
FIGURE 3-3:
© 2007 Microchip Technology Inc.
PGCx
PGDx
Fetch REGOUT Control Code
Execute Previous Instruction, CPU Held in Idle
REGOUT SERIAL INSTRUCTION
EXECUTION
1
1
0
2
PGDx = Input
0
3
0
REGOUT SERIAL EXECUTION
4
P4
1
2
7
8
P5
LSb
1
1
2
2
3
3
4
PIC24FJXXXGA1/GB1
Shift Out VISI Register<15:0>
4
5
PGDx = Output
...
Note 1: After the contents of VISI are shifted out,
6
10
11
2: Data changes on the falling edge and
11
12
the
maintain PGDx as an output until the first
rising edge of the next clock is received.
latches on the rising edge of PGCx. For
all
Significant bit (LSb) is transmitted first.
12
13
13
14
data
PIC24FJXXXGA1/GB1
14
15 16
MSb
transmissions,
P4A
0
No Execution Takes Place,
Fetch Next Control Code
1
PGDx = Input
0
2
DS39907A-page 13
0
3
the
0
4
devices
Least

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