PIC16F876AT-E/SS Microchip Technology, PIC16F876AT-E/SS Datasheet - Page 2

IC MCU FLASH 8KX14 W/AD 28-SSOP

PIC16F876AT-E/SS

Manufacturer Part Number
PIC16F876AT-E/SS
Description
IC MCU FLASH 8KX14 W/AD 28-SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F876AT-E/SS

Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC16F87XA
MOVF
Syntax:
Operands:
Operation:
Status Affected:
Description:
MOVLW
Syntax:
Operands:
Operation:
Status Affected:
Description:
MOVWF
Syntax:
Operands:
Operation:
Status Affected:
Description:
DS80276A-page 2
Move f
[ label ]
0 ≤ f ≤ 127
d ∈ [0,1]
(f) → (destination)
Z
The contents of register ‘f’ are
moved to a destination dependant
upon the status of ‘d’. If d = 0,
destination is W register. If d = 1,
the destination is file register ‘f’
itself. d = 1 is useful to test a file
register, since status flag Z is
affected.
Move Literal to W
[ label ]
0 ≤ k ≤ 255
k → (W)
None
The eight bit literal ‘k’ is loaded
into W register. The don’t cares
will assemble as 0’s.
Move W to f
[ label ]
0 ≤ f ≤ 127
(W) → (f)
None
Move data from W register to
register ‘f’.
MOVF f,d
MOVLW k
MOVWF
f
NOP
Syntax:
Operands:
Operation:
Status Affected:
Description:
RETFIE
Syntax:
Operands:
Operation:
Status Affected:
RETLW
Syntax:
Operands:
Operation:
Status Affected:
Description:
No Operation
[ label ]
None
No operation
None
No operation.
Return from Interrupt
[ label ]
None
TOS → PC,
1 → GIE
None
Return with Literal in W
[ label ]
0 ≤ k ≤ 255
k → (W);
TOS → PC
None
The W register is loaded with the
eight bit literal ‘k’. The program
counter is loaded from the top of
the stack (the return address).
This is a two-cycle instruction.
© 2006 Microchip Technology Inc.
NOP
RETFIE
RETLW k

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