PIC16C72-20/SS Microchip Technology, PIC16C72-20/SS Datasheet - Page 2

• Manufacturer Part Number: PIC16C72-20/SS
• Description: IC MCU OTP 2KX14 A/D PWM 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C72-20/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C, SPI, SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: 0 C
• On-chip Adc: 5 bit
• For Use With: 309-1025 - ADAPTER 28-SSOP TO 28-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC16C72-20/SSR; PIC16C72-20/SSR

PIC16C72
3. Module: CCP (Compare Mode)
4. Module: SSP Module (I
DS80092A-page 2
The special event trigger of the Compare mode
may not occur if both of the following conditions
exist:
•
•
The interrupt for the compare event will still be
generated, but no special event trigger will occur.
Work around
Use the Interrupt Service Routine instead of using
the special event trigger to reset Timer1 (and start
an A/D conversion, if applicable).
If the bus is active when the I
and the next 8 bits of data on the bus match the
address of the device, then the SSP module will
generate an Acknowledge pulse.
Work around
Before enabling the I
is not active.
CCP1
Unit
An instruction, one cycle (T
Timer1/Compare register match has literal
data equal to the address of a CCP register
being used. Specific cases include:
An instruction in the same cycle as a
Timer1/Compare register match has an
MSb of ‘0’.
CCP1CON
Register
CCPR1H
CCPR1L
2
C mode, ensure that the bus
2
C™ mode)
2
C mode is enabled,
CY
) prior to a
Literal Data
15h
16h
17h
5. Module: SSP (SPI Mode)
FIGURE 1:
EXAMPLE 1:
6. Module: Timer0
LOOP BTFSS SSPSTAT, BF
When the SPI is using Timer2/2 as the clock
source, a shorter than expected SCK pulse may
occur on the first bit of the transmitted/received
data (Figure 1).
Work around
To avoid producing the short pulse, turn off Timer2
and clear the TMR2 register, load the SSPBUF
with the data to transmit, and then turn Timer2
back on. Refer to Example 1 for sample code.
The TMR0 register may increment when the WDT
postscaler is switched to the Timer0 prescaler. If
TMR0 = FFh, this will cause TMR0 to overflow
(setting T0IF).
Work around
Follow the following sequence:
a) Read the 8-bit TMR0 register into the
b) Clear the TMR0 register
c) Assign WDT postscaler to Timer0
d) Write W register to TMR0
SD0
SCK
BSF
GOTO
BCF
MOVF
MOVWF RXDATA
MOVF
BCF
CLR
MOVWF SSPBUF
BSF
W register
Write SSPBUF
STATUS, RP0
LOOP
STATUS, RP0
SSPBUF, W
TXDATA, W
T2CON, TMR2ON
TMR2
T2CON, TMR2ON
SCK PULSE VARIATION
USING TIMER2/2
bit0=1 bit1=0 bit2=1 . . . .
SHORT SCK PULSE
AVOIDING THE INITIAL
 2001 Microchip Technology Inc.
;Bank 1
;Data received?
;(Xmit complete?)
;No
;Bank 0
;W = SSPBUF
;Save in user RAM
;W = TXDATA
;Timer2 off
;Clear Timer2
;Xmit New data
;Timer2 on