DSPIC33FJ128GP708T-I/PT Microchip Technology, DSPIC33FJ128GP708T-I/PT Datasheet - Page 5

• Manufacturer Part Number: DSPIC33FJ128GP708T-I/PT
• Description: IC DSPIC MCU/DSP 128K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP708T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• For Use With: DM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164328 - MODULE SKT FOR 80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

TABLE 2:
© 2010 Microchip Technology Inc.
Note 1:
Module
ECAN
UART
ADC
DCI
SPI
SPI
I
I/O
2
C
Only those issues indicated in the last column apply to the current silicon revision.
Transmission
Consumption
Sleep Mode
Generation
SDO1 Pin
Operation
Character
FRMDLY
Transmit
SILICON ISSUE SUMMARY (CONTINUED)
Feature
in Sleep
Current
Break
Slave
Mode
Data
—
Number
Item
54.
55.
56.
57.
58.
59.
60.
61.
The WAKIF bit in the CxINTF register cannot be cleared by
software instruction after the device is interrupted from Sleep
due to activity on the CAN bus.
After the ACKSTAT bit is set when receiving a NACK, it may
be cleared by the reception of a Start or Stop bit.
Writing to the SPIxBUF register as soon as TBF bit is cleared
will cause the SPI module to ignore written data.
When using more than one transmit buffer, the DCI module
will corrupt the data transmitted on the CSDO line.
The UART module will not generate back-to-back Break
characters.
The SDO1 pin may toggle while the device is being
programmed via PGECx/PGEDx pin pairs.
The SPI communication in Framed mode does not function
correctly if the Slave SPI frame delay bit (FRMDLY) is set to
‘1’.
If the ADC module is in an enabled state when the device
enters Sleep Mode, the power-down current (I
device may exceed the device data sheet specifications.
Issue Summary
PD
) of the
DS80446D-page 5
Revisions
A2 A3 A4
X
X
X
X
X
X
X
X
Affected
X
X
X
X
X
X
X
X
(1)
X
X
X
X
X
X
X
X