PIC18LF2420-I/SP Microchip Technology, PIC18LF2420-I/SP Datasheet - Page 58

• Manufacturer Part Number: PIC18LF2420-I/SP
• Description: IC MCU FLASH 8KX16 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2420-I/SP

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 25
• Interface Type: I2C/SPI/USART
• On-chip Adc: 10-chx10-bit
• Number Of Timers: 4
• Core: PIC
• Processor Series: PIC18LF
• Maximum Clock Frequency: 40 MHz
• Data Ram Size: 768 B
• Data Rom Size: 256 B
• Mounting Style: Through Hole
• Height: 3.3 mm
• Length: 34.67 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 7.24 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2420/2520/4420/4520
5.1.2.4
Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit in
Configuration Register 4L. When STVREN is set, a full
or underflow will set the appropriate STKFUL or
STKUNF bit and then cause a device Reset. When
STVREN is cleared, a full or underflow condition will set
the appropriate STKFUL or STKUNF bit but not cause
a device Reset. The STKFUL or STKUNF bits are
cleared by the user software or a Power-on Reset.
5.1.3
A Fast Register Stack is provided for the STATUS,
WREG and BSR registers, to provide a “fast return”
option for interrupts. The stack for each register is only
one level deep and is neither readable nor writable. It is
loaded with the current value of the corresponding reg-
ister when the processor vectors for an interrupt. All
interrupt sources will push values into the stack regis-
ters. The values in the registers are then loaded back
into their associated registers if the RETFIE, FAST
instruction is used to return from the interrupt.
If both low and high-priority interrupts are enabled, the
stack registers cannot be used reliably to return from
low-priority interrupts. If a high-priority interrupt occurs
while servicing a low-priority interrupt, the stack regis-
ter values stored by the low-priority interrupt will be
overwritten. In these cases, users must save the key
registers in software during a low-priority interrupt.
If interrupt priority is not used, all interrupts may use the
Fast Register Stack for returns from interrupt. If no
interrupts are used, the Fast Register Stack can be
used to restore the STATUS, WREG and BSR registers
at the end of a subroutine call. To use the Fast Register
Stack for a subroutine call, a CALL label, FAST
instruction must be executed to save the STATUS,
WREG and BSR registers to the Fast Register Stack. A
RETURN, FAST instruction is then executed to restore
these registers from the Fast Register Stack.
Example 5-1 shows a source code example that uses
the Fast Register Stack during a subroutine call and
return.
EXAMPLE 5-1:
DS39631E-page 56
CALL SUB1, FAST
SUB1
RETURN, FAST
•
•
•
•
FAST REGISTER STACK
Stack Full and Underflow Resets
FAST REGISTER STACK
CODE EXAMPLE
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
5.1.4
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:
• Computed GOTO
• Table Reads
5.1.4.1
A computed GOTO is accomplished by adding an offset
to the program counter. An example is shown in
Example 5-2.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nn instructions. The
W register is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW
instructions that returns the value ‘nn’ to the calling
function.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSb = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
EXAMPLE 5-2:
5.1.4.2
A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
Look-up table data may be stored two bytes per pro-
gram word by using table reads and writes. The Table
Pointer (TBLPTR) register specifies the byte address
and the Table Latch (TABLAT) register contains the
data that is read from or written to program memory.
Data is transferred to or from program memory one
byte at a time.
Table read and table write operations are discussed
further in Section 6.1 “Table Reads and Table
Writes”.
ORG
TABLE
MOVF
CALL
nn00h
ADDWF
RETLW
RETLW
RETLW
.
.
.
LOOK-UP TABLES IN PROGRAM
MEMORY
Computed GOTO
Table Reads and Table Writes
OFFSET, W
TABLE
PCL
nnh
nnh
nnh
COMPUTED GOTO USING
AN OFFSET VALUE
© 2008 Microchip Technology Inc.
nn