PIC18F452-I/PG Microchip Technology, PIC18F452-I/PG Datasheet - Page 4

• Manufacturer Part Number: PIC18F452-I/PG
• Description: IC MCU FLASH 16KX16 W/AD 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F452-I/PG

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• For Use With: ACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18FXX2/XX8
Users may store identification information (ID) in eight
ID registers. These ID registers are mapped in
addresses 200000h through 200007h. The ID locations
read out normally, even after code protection is applied.
Locations 300001h through 30000Dh are reserved for
the configuration bits. These bits may be set to select
various device options, and are described in
Section 5.0. These configuration bits read out normally
even after code protected.
Locations 3FFFFEh and 3FFFFFh are reserved for the
device ID bits. These bits may be used by the program-
mer to identify what device type is being programmed,
and are described in Section 5.0. These configuration
bits read out normally even after code protection.
FIGURE 2-3:
DS39576C-page 4
2FFFFFh
Note:
000000h
01FFFFh
1FFFFFh
3FFFFFh
Sizes of memory areas are not to scale.
Unimplemented
Code Memory
Configuration
Read as ‘0’
and ID
Space
CONFIGURATION AND ID LOCATIONS FOR PIC18FXX2/XX8 DEVICES
2.3.1
Memory in the address space 000000h to 3FFFFFh is
addressed via the Table Pointer, which is comprised of
three pointer registers:
• TBLPTRU, at address 0FF8h
• TBLPTRH, at address 0FF7h
• TBLPTRL, at address 0FF6h
The 4-bit command, ‘0000’ (Core Instruction), is used
to load the Table Pointer prior to using many Read or
Write operations.
Addr[21:16]
TBLPTRU
MEMORY ADDRESS POINTER
Addr[15:8]
ID Location 1
ID Location 2
ID Location 3
ID Location 4
ID Location 5
ID Location 6
ID Location 7
ID Location 8
TBLPTRH
CONFIG1H
CONFIG2H
CONFIG3H
CONFIG4H
CONFIG5H
CONFIG6H
CONFIG7H
CONFIG1L
CONFIG2L
CONFIG3L
CONFIG4L
CONFIG5L
CONFIG6L
CONFIG7L
Device ID1
Device ID2
 2010 Microchip Technology Inc.
3FFFFEh
3FFFFFh
30000Ah
30000Bh
30000Ch
30000Dh
200000h
200001h
200002h
200003h
200004h
200005h
200006h
200007h
300000h
300001h
300002h
300003h
300004h
300005h
300006h
300007h
300008h
300009h
TBLPTRL
Addr[7:0]