PIC24HJ64GP504-I/PT Microchip Technology, PIC24HJ64GP504-I/PT Datasheet - Page 4

• Manufacturer Part Number: PIC24HJ64GP504-I/PT
• Description: IC PIC MCU FLASH 64K 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ64GP504-I/PT

• Core Size: 16-Bit
• Program Memory Size: 64KB (22K x 24)
• Core Processor: PIC
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 13x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC24
• No. Of I/o's: 35
• Ram Memory Size: 4KB
• Cpu Speed: 40MIPS
• No. Of Timers: 7
• No. Of Pwm Channels: 4
• Embedded Interface Type: CAN, I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

11. Module: UART (UxE Interrupt)
12. Module: UART (IrDA)
13. Module: Comparator
14. Module: Internal Voltage Regulator
15. Module: Product Identification
DS80373B-page 4
The UART error interrupt may not occur, or may
occur at an incorrect time, if multiple errors occur
during a short period of time.
Work around
Read the error flags in the UxSTA register
whenever a byte is received to verify the error
status. In most cases, these bits will be correct,
even if the UART error interrupt fails to occur.
When the UART is operating in 8-bit mode
(PDSEL = 0x) and using the IrDA encoder/decoder
(IREN = 1), the module incorrectly transmits a data
payload of 80h as 00h.
Work around
None.
If CMCON<CxOUTEN> is set and the Comparator
module
remappable comparator output pins, C1OUT and
C2OUT, cannot be used as General Purpose I/O
pins.
Work around
When the Comparator module is disabled the
CMCON<CxOUTEN> bit should be reset so that
the remappable comparator output pins C1OUT
and C2OUT are not driven onto the output pad.
When the VREGS (RCON<8>) bit is set to a logic
‘0’, higher sleep current may be observed.
Work around
Ensure VREGS (RCON<8>) bit is set to a logic ‘1’
for device Sleep mode operation.
Revision A2 devices marked as extended
temperature range (E) devices, support only
industrial temperature range (I).
Work around
Use Revision A3 devices marked as extended
temperature range (E) devices.
CMCON<CxEN>
is
disabled,
the
16. Module: PSV Operations
17. Module: ECAN
18. Module: ECAN
An address error trap occurs in certain addressing
modes when accessing the first four bytes of an
PSV page. This only occurs when using the
following addressing modes:
• MOV.D
• Register indirect addressing (word or byte
Work around
Do not perform PSV accesses to any of the first
four bytes using the above addressing modes. For
applications using the C language, MPLAB C30
version 3.11 or higher, provides the following
command-line switch that implements a work
around for the erratum.
-merrata=psv_trap
Refer to the readme.txt file in the MPLAB C30
v3.11 tool suite for further details.
The ECAN module may not store received data in
the correct location. When this occurs, the receive
buffers will become corrupted. In addition, it is also
possible for the transmit buffers to become
corrupted. This issue is more likely to occur as the
CAN bus speed approaches 1 Mbps.
Work around
None.
The ECAN module does not generate a CAN
event interrupt when coming out of Disable mode
on bus wake-up activity even if the WAKIE bit in
the CiINTE register is set. The WAKIF bit in the
CiINTF register will reflect the correct status. The
CAN event interrupt occurs only if the device was
in Sleep mode when the bus wake-up activity
occurred.
Work around
When placing the ECAN module in Disable mode,
place the device in Sleep mode to be able to
generate the CAN event interrupt on bus wake-up
activity. If it is not possible to place the device in
Sleep mode, poll the WAKIF bit in the CiINTF
register to track bus wake-up activity.
mode) with pre/post-decrement
© 2008 Microchip Technology Inc.