PIC16LF874A-I/L Microchip Technology, PIC16LF874A-I/L Datasheet - Page 156

• Manufacturer Part Number: PIC16LF874A-I/L
• Description: IC MCU FLASH 4KX14 EE A/D 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF874A-I/L

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Controller Family/series: PIC16LF
• No. Of I/o's: 33
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 192Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC16LF874A-I/LR; PIC16LF874A-I/LR; PIC16LF874AI/L

PIC16F87XA
14.11.1
External interrupt on the RB0/INT pin is edge triggered,
either rising if bit INTEDG (OPTION_REG<6>) is set or
falling if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit, INTF
(INTCON<1>), is set. This interrupt can be disabled by
clearing enable bit, INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT
interrupt can wake-up the processor from Sleep if bit
INTE was set prior to going into Sleep. The status of
global interrupt enable bit, GIE, decides whether or not
the processor branches to the interrupt vector following
wake-up. See Section 14.14 “Power-down Mode
(Sleep)” for details on Sleep mode.
14.11.2
An overflow (FFh
flag bit, TMR0IF (INTCON<2>). The interrupt can be
enabled/disabled
TMR0IE (INTCON<5>). See Section 5.0 “Timer0
Module”.
14.11.3
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<4>). See
Section 4.2 “PORTB and the TRISB Register”.
EXAMPLE 14-1:
DS39582B-page 154
MOVWF
SWAPF
CLRF
MOVWF
MOVF
MOVWF
CLRF
:
:(ISR)
:
MOVF
MOVWF
SWAPF
MOVWF
SWAPF
SWAPF
INT INTERRUPT
TMR0 INTERRUPT
PORTB INTCON CHANGE
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
PCLATH_TEMP, W
PCLATH
STATUS_TEMP,W
STATUS
W_TEMP,F
W_TEMP,W
by
00h) in the TMR0 register will set
SAVING STATUS, W AND PCLATH REGISTERS IN RAM
setting/clearing
;Copy W to TEMP register
;Swap status to be saved into W
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
;Save status to bank zero STATUS_TEMP register
;Only required if using pages 1, 2 and/or 3
;Save PCLATH into W
;Page zero, regardless of current page
;(Insert user code here)
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
enable
bit,
14.12 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt (i.e., W register and Status
register). This will have to be implemented in software.
For the PIC16F873A/874A devices, the register
W_TEMP must be defined in both Banks 0 and 1 and
must be defined at the same offset from the bank base
address (i.e., If W_TEMP is defined at 0x20 in Bank 0,
it must also be defined at 0xA0 in Bank 1). The regis-
ters, PCLATH_TEMP and STATUS_TEMP, are only
defined in Bank 0.
Since the upper 16 bytes of each bank are common in
the PIC16F876A/877A devices, temporary holding reg-
isters, W_TEMP, STATUS_TEMP and PCLATH_TEMP,
should be placed in here. These 16 locations don’t
require banking and therefore, make it easier for con-
text save and restore. The same code shown in
Example 14-1 can be used.
 2003 Microchip Technology Inc.