AT32UC3A364-CTUT Atmel, AT32UC3A364-CTUT Datasheet - Page 40

• Manufacturer Part Number: AT32UC3A364-CTUT
• Description: IC MCU 64KB FLASH 144TBGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-TBGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, I2S, JTAG, SPI, USART
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.4.11
8.4.12
8.4.13
32072C–AVR32–2010/03
Peripheral DMA Controller
DMA Controller
General-Purpose Input/Output Controller
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Serial Peripheral Interface
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Energy-saving capabilities
Error detection
SDRAM power-up initialization by software
CAS latency of one, two, and three supported
Auto Precharge command not used
Multiple channels
Generates transfers to/from peripherals such as USART and SPI
Two address pointers/counters per channel allowing double buffering
Performance monitors to measure average and maximum transfer latency
2 HSB Master Interfaces
Channels
Software and Hardware Handshaking Interfaces
Memory/Non-Memory Peripherals to Memory/Non-Memory Peripherals Transfer
Single-block DMA Transfer
Multi-block DMA Transfer
DMA Controller is Always the Flow Controller
Additional Features
Each I/O line of the GPIO features:
Configurable pin-change, rising-edge or falling-edge interrupt on any I/O line
A glitch filter providing rejection of pulses shorter than one clock cycle
Input visibility and output control
Multiplexing of up to four peripheral functions per I/O line
Programmable internal pull-up resistor
Compatible with an embedded 32-bit microcontroller
Supports communication with serial external devices
– Timing parameters specified by software
– Automatic refresh operation, refresh rate is programmable
– Automatic update of DS, TCR and PASR parameters (mobile SDRAM devices)
– Self-refresh, power-down, and deep power-down modes supported
– Supports mobile SDRAM devices
– Refresh error interrupt
– 9 Hardware Handshaking Interfaces
– Linked Lists
– Auto-Reloading
– Contiguous Blocks
– Scatter and Gather Operations
– Channel Locking
– Bus Locking
– FIFO Mode
– Pseudo Fly-by Operation
– Four chip selects with external decoder support allow communication with up to 15
peripherals
AT32UC3A3/A4
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