AT32UC3A364S-CTUR Atmel, AT32UC3A364S-CTUR Datasheet
AT32UC3A364S-CTUR
Specifications of AT32UC3A364S-CTUR
Related parts for AT32UC3A364S-CTUR
AT32UC3A364S-CTUR Summary of contents
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... Memory Stick: Standard Format V1.40, PRO Format V1.00, Micro – IDE Interface • One Advanced Encryption System (AES) for AT32UC3A3256S, AT32UC3A3128S and AT32UC3A364S – 256-, 192-, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications – Buffer Encryption/Decryption Capabilities • ...
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Support for Hardware Handshaking, RS485 Interfaces and Modem Line • Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals • One Synchronous Serial Protocol Controller – Supports I2S and Generic Frame-Based Protocols • Two Master/Slave Two-Wire Interface (TWI), ...
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Description The AT32UC3A3 is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 66MHz. AVR32 high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular empha- sis ...
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Blockdiagram Figure 2-1. Blockdiagram TCK JTAG TDO INTERFACE TDI TMS MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N VBG VBUS USB HS DH+,DL+ DH-,DL- INTERFACE ID VBOF DMA DMACA AES 32KB RAM 32KB RAM CLK CMD[1..0] DATA[15.. EXTINT[7..0] ...
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Processor and Architecture 2.1.1 AVR32 UC CPU • 32-bit load/store AVR32A RISC architecture – 15 general-purpose 32-bit registers – 32-bit Stack Pointer, Program Counter and Link Register reside in register file – Fully orthogonal instruction set – Privileged and ...
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Signals Description The following table gives details on the signal name classified by peripheral Table 3-1. Signal Description List Signal Name Function VDDIO I/O Power Supply VDDANA Analog Power Supply VDDIN Voltage Regulator Input Supply ONREG Voltage Regulator ON/OFF ...
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Table 3-1. Signal Description List Signal Name Function GCLK[2:0] Generic Clock Pins RESET_N Reset Pin DMAACK[1:0] DMA Acknowledge DMARQ[1:0] DMA Requests EXTINT[7:0] External Interrupt Pins KPS0 - KPS7 Keypad Scan Pins NMI_N Non-Maskable Interrupt Pin General Purpose Input/Output pin - ...
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Table 3-1. Signal Description List Signal Name Function RAS Row Signal SDA10 SDRAM Address 10 Line SDCK SDRAM Clock SDCKE SDRAM Clock Enable SDCS SDRAM Chip Select SDWE SDRAM Write Enable CLK Multimedia Card Clock CMD[1:0] Multimedia Card Command DATA[15:0] ...
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Table 3-1. Signal Description List Signal Name Function B2 Channel 2 Line B CLK0 Channel 0 External Clock Input CLK1 Channel 1 External Clock Input CLK2 Channel 2 External Clock Input SCL Serial Clock SDA Serial Data Universal Synchronous Asynchronous ...
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Table 3-1. Signal Description List Signal Name Function HSDP USB High Speed Data + USB_VBIAS USB VBIAS reference USB_VBUS USB VBUS for OTG feature 32072AS–AVR32–03/09 AT32UC3A3 Active Type Level Comments Analog Connect to the ground through a Analog 6810ohms (+/- ...
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Package and Pinout 4.1 Package The device pins are multiplexed with peripheral functions as described in the Peripheral Multi- plexing on I/O Line section. Figure 4-1. TBGA144 Pinout (top view) Table 4-1. BGA144 Package Pinout A1.. ...
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Figure 4-2. LQFP144 Pinout Table 4-2. Package Pinout 1 USB_VBUS 2 VDDIO 3 USB_VBIAS 4 GNDIO 5 DMHS 6 DPHS 7 GNDIO 8 DMFS 9 DPFS 10 VDDIO 11 PB08 12 PC05 13 PC04 14 PA30 15 PA02 16 PB10 ...
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Table 4-2. Package Pinout 27 PB01 28 PA28 29 PA31 30 PB00 31 PB11 32 PX16 33 PX13 34 PX12 35 PX19 36 PX40 4.2 Peripheral Multiplexing on I/O lines Each GPIO line can be assigned to one of 4 ...
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Table 4-3. GPIO Controller Function Multiplexing J9 113 PA20 H9 109 PA21 H10 110 PA22 G8 111 PA23 G9 112 PA24 E9 119 PA25 D9 120 PA26 A4 26 PA27 A3 28 PA28 A6 23 PA29 C7 14 PA30 B3 ...
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Table 4-3. GPIO Controller Function Multiplexing J2 62 PX02 K1 63 PX03 J1 60 PX04 G2 58 PX05 F3 53 PX06 F2 54 PX07 D1 50 PX08 C1 49 PX09 B1 37 PX10 L1 67 PX11 D6 34 PX12 C6 ...
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Table 4-3. GPIO Controller Function Multiplexing E1 51 PX38 F1 52 PX39 A1 36 PX40 M2 71 PX41 M3 69 PX42 L7 88 PX43 K2 66 PX44 L3 70 PX45 K4 74 PX46 D4 39 PX47 F5 41 PX48 F4 ...
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Signal Descriptions The following table gives details on signal name classified by peripheral. Table 4-5. Signal Description List Signal Name Function VDDIO I/O Power Supply VDDANA Analog Power Supply VDDIN Voltage Regulator Input Supply ONREG Voltage Regulator ON/OFF VDDCORE ...
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Table 4-5. Signal Description List Signal Name Function GCLK[2:0] Generic Clock Pins RESET_N Reset Pin DMAACK[1:0] DMA Acknowledge DMARQ[1:0] DMA Requests EXTINT[7:0] External Interrupt Pins KPS0 - KPS7 Keypad Scan Pins NMI_N Non-Maskable Interrupt Pin General Purpose Input/Output pin - ...
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Table 4-5. Signal Description List Signal Name Function RAS Row Signal SDA10 SDRAM Address 10 Line SDCK SDRAM Clock SDCKE SDRAM Clock Enable SDCS SDRAM Chip Select SDWE SDRAM Write Enable CLK Multimedia Card Clock CMD[1:0] Multimedia Card Command DATA[15:0] ...
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Table 4-5. Signal Description List Signal Name Function B2 Channel 2 Line B CLK0 Channel 0 External Clock Input CLK1 Channel 1 External Clock Input CLK2 Channel 2 External Clock Input SCL Serial Clock SDA Serial Data Universal Synchronous Asynchronous ...
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Table 4-5. Signal Description List Signal Name Function HSDP USB High Speed Data + USB_VBIAS USB VBIAS reference USB_VBUS USB VBUS for OTG feature 4.3.1 JTAG Pins TMS and TDI pins have pull-up resistors. TDO pin is an output, driven ...
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Power Considerations 4.4.1 Power Supplies The AT32UC3A3 has several types of power supply pins: • VDDIO: Powers I/O lines. Voltage is 3.3V nominal • VDDANA: Powers the ADC Voltage and provides the ADVREF voltage is 3.3V nominal • VDDIN: ...
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Power Considerations 5.1 Power Supplies The AT32UC3A3 has several types of power supply pins: • VDDIO: Powers I/O lines. Voltage is 3.3V nominal • VDDANA: Powers the ADC Voltage and provides the ADVREF voltage is 3.3V nominal • VDDIN: ...
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I/O Line Considerations 6.1 JTAG Pins TMS and TDI pins have pull-up resistors. TDO pin is an output, driven VDDIO, and has no pull-up resistor. 6.2 RESET_N Pin The RESET_N pin is a schmitt input and ...
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Memories 7.1 Embedded Memories • Internal High-Speed Flash – 256KBytes (AT32UC3A3256/S) – 128Kbytes (AT32UC3A3128/S) – 64Kbytes (AT32UC3A364/S) • Internal High-Speed SRAM – 64KBytes, Single-cycle access at full speed on CPU Local Bus and accessible through the High Speed Bud ...
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Table 7-1. Device Embedded System SRAM 1 HSB-PB Bridge A HSB-PB Bridge B 7.3 Peripheral Address Map Table 7-2. Peripheral Address Mapping Address 0xFF100000 0xFF200000 0xFFFD0000 0xFFFE0000 0xFFFE1000 0xFFFE1400 0xFFFE1C00 0xFFFE2000 0xFFFE2400 0xFFFE2800 0xFFFE4000 0xFFFE8000 0xFFFF0000 0xFFFF0800 32072AS–AVR32–03/09 AT32UC3A3 Physical ...
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Table 7-2. Peripheral Address Mapping 0xFFFF0C00 0xFFFF0D00 0xFFFF0D30 0xFFFF0D80 0xFFFF1000 0xFFFF1400 0xFFFF1800 0xFFFF1C00 0xFFFF2000 0xFFFF2400 0xFFFF2800 0xFFFF2C00 0xFFFF3000 0xFFFF3400 0xFFFF3800 0xFFFF3C00 0xFFFF4000 0xFFFF4400 0xFFFF4800 32072AS–AVR32–03/09 PM Power Manager - PM RTC Real Time Counter - RTC WDT Watchdog Timer - ...
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Table 7-2. Peripheral Address Mapping 0xFFFF4c00 0xFFFF5000 0xFFFF5400 7.4 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus. These registers can ...
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Peripherals 8.1 Clock Connections 8.1.1 Timer/Counters Each Timer/Counter channel can independently select an internal or external clock source for its counter: Table 8-1. Source Internal External 8.2 Peripheral Multiplexing on I/O lines Each GPIO line can be assigned to ...
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Table 8-2. GPIO Controller Function Multiplexing J6 100 PA14 J7 101 PA15 F12 128 PA16 H7 116 PA17 K8 115 PA18 J8 114 PA19 J9 113 PA20 H9 109 PA21 H10 110 PA22 G8 111 PA23 G9 112 PA24 E9 ...
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Table 8-2. GPIO Controller Function Multiplexing H6 99 PC01 A7 18 PC02 B7 19 PC03 A8 13 PC04 A9 12 PC05 G1 55 PX00 H1 59 PX01 J2 62 PX02 K1 63 PX03 J1 60 PX04 G2 58 PX05 F3 ...
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Table 8-2. GPIO Controller Function Multiplexing K11 94 PX29 M11 96 PX30 M10 97 PX31 M9 93 PX32 M12 95 PX33 J3 61 PX34 C2 38 PX35 D3 44 PX36 D2 45 PX37 E1 51 PX38 F1 52 PX39 A1 ...
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Table 8-3. 32072AS–AVR32–03/09 Oscillator Pinout AT32UC3A3 PC00 xin32 PC03 xout0 PC05 xout1 PC01 xout32 33 ...
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Peripheral overview 8.4.1 Power Manager • Controls integrated oscillators and PLLs • Generates clocks and resets for digital logic • Supports 2 crystal oscillators 4MHZ-16MHz • Supports 2 PLLs 48-150MHz • Supports 32KHz ultra-low power oscillator • Integrated low-power ...
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groups of interrupts with interrupt requests in each 8.4.5 External Interrupts Controller • Dedicated interrupt request for each interrupt • Individually maskable interrupts • Interrupt on rising or falling edge • Interrupt on ...
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One Cycle Latency for the First Access of a Burst • Zero Cycle Latency for Default Master • One Special Function Register for Each Slave (Not dedicated) 8.4.8 External Bus Interface • Optimized for application memory space support • ...
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Timing parameters specified by software – Automatic refresh operation, refresh rate is programmable – Automatic update of DS, TCR and PASR parameters (mobile SDRAM devices) • Energy-saving capabilities – Self-refresh, power-down, and deep power-down modes supported – Supports mobile ...
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Serial memories, such as DataFlash and 3-wire EEPROMs – Serial peripherals, such as ADCs, DACs, LCD controllers, CAN controllers and Sensors – External co-processors • Master or Slave Serial Peripheral Bus Interface – 16-bit programmable data ...
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... Compatible with PMBus • Compatible with Atmel Two-Wire Interface Serial Memories • DMA interface for reducing CPU load • Arbitrary transfer lengths, including 0 data bytes • Optional clock stretching if transmit or receive buffers not ready for data transfer 8.4.16 Synchronous Serial Controller • ...
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Full LIN error checking and reporting – Frame Slot Mode: the Master allocates slots to the scheduled frames automatically. – Generation of the Wakeup signal • Test Modes – Remote Loopback, Local Loopback, Automatic Echo • Supports Connection of ...
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HSB Bus Performance Monitor • Allows performance monitoring of High Speed Bus master interfaces – masters can be monitored – Peripheral Bus access to monitor registers • The following is monitored – Data transfer cycles – ...
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Advanced Encryption Standart • Compliant with FIPS Publication 197, Advanced Encryption Standard (AES) • 128-bit/192-bit/256-bit cryptographic key • 12/14/16 clock cycles encryption/decryption processing time with a 128-bit/192-bit/256-bit cryptographic key • Support of the five standard modes of operation specified ...
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Boot Sequence This chapter summarizes the boot sequence of the AT32UC3A3. The behavior after power-up is controlled by the Power Manager. For specific details, refer to on page 9.1 Starting of Clocks After power-up, the device will be held ...
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Electrical Characteristics 10.1 Absolute Maximum Ratings* Operating Temperature.................................... -40°C to +85°C Storage Temperature .......................................................... ....- 60°C to +150°C Voltage on Input Pin with respect to Ground ........................................-0.3V to 3.6V Maximum Operating Voltage (VDDCORE) ..................... 1.95V Maximum Operating Voltage (VDDIO).............................. ...
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Table 10-1. PIN PA00 PA01 PA02 PA03 PA04 PA05 PA06 PA07 PA08 PA09 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PB00 PB01 PB02 PB03 PB04 ...
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Regulator characteristics 10.3.1 Electrical characteristics Symbol Parameter V Supply voltage (input) VDDIN V Supply voltage (output) VDDCORE Maximum DC output current with V I OUT Maximum DC output current with V 10.3.2 Decoupling requirements Symbol Parameter C Input Regulator ...
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Figure 10-1. Measurement setup 32072AS–AVR32–03/09 VDDANA Amp0 VDDIO VDDIN Amp1 Internal Voltage Regulator VDDCORE GNDCORE GNDPLL AT32UC3A3 47 ...
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These figures represent the power consumption measured on the power supplies. Table 10-3. Power Consumption for Different Modes Mode Conditions CPU running from flash. CPU clocked from PLL0 at f MHz Voltage regulator is on. XIN0 : external clock. XIN1 ...
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Ambient Temperature = 25°C 10.5.1 CPU/HSB Clock Characteristics Table 10-5. Core Clock Waveform Parameters Symbol Parameter 1/(t ) CPU Clock Frequency CPCPU t CPU Clock Period CPCPU 10.5.2 PBA Clock Characteristics Table 10-6. PBA Clock Waveform Parameters Symbol Parameter ...
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... Table 10-11. Phase Lock Loop Characteristics Symbol Parameter F Output Frequency OUT F Input Frequency IN I Current Consumption PLL Note: 1. Startup time depends on PLL RC filter. A calculation tool is provided by Atmel. 32072AS–AVR32–03/09 Conditions ( TBD kΩ TBD the equivalent load capacitance. L Conditions Active mode @TBD MHz ...
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ADC Characteristics Table 10-12. Channel Conversion Time and ADC Clock Parameter ADC Clock Frequency ADC Clock Frequency Startup Time Track and Hold Acquisition Time Conversion Time Conversion Time Throughput Rate Throughput Rate Notes: 1. Corresponds to 13 clock cycles ...
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USB Transceiver Characteristics 10.8.1 Electrical Characteristics Table 10-15. Electrical Parameters Symbol Parameter Input Levels V Low Level IL V High Level IH V Differential Input Sensivity DI Differential Input Common V CM Mode Range C Transceiver capacitance IN I ...
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EBI Timings These timings are given for worst case process 85⋅C, VDDCORE = 1.65V, VDDIO = 3V and 40 pF load capacitance. Table 10-18. SMC Clock Signal. Symbol Parameter 1/(t ) SMC Controller Clock Frequency CPSMC Note: ...
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Table 10-20. SMC Read Signals with no Hold Settings Symbol Parameter SMC Data Setup before NRD High 19 Data Hold after NRD High SMC 20 SMC Data Setup before NCS High 21 SMC Data Hold after NCS High 22 Table ...
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Table 10-22. SMC Write Signals with No Hold Settings (NWE Controlled only). Symbol Parameter NWE Rising to A2-A25 Valid SMC 37 NWE Rising to NBS0/A0 Valid SMC 38 NWE Rising to NBS1 Change SMC 39 NWE Rising to A1/NBS2 Change ...
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Figure 10-3. SMC Signals for NRD and NRW Controlled Accesses. A2-A25 A0/A1/NBS[3:0] NCS SMC9 NRD SMC19 D0 - D15 NWE 10.9.1 SDRAM Signals These timings are given for 10 pF load on SDCK and other signals. Table ...
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Table 10-24. SDRAM Clock Signal. Symbol SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC 32072AS–AVR32–03/09 Parameter Address Change before SDCK Rising Edge 11 Address Change after SDCK Rising Edge 12 Bank Change before SDCK ...
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Figure 10-4. SDRAMC Signals relative to SDCK. SDCK SDRAMC SDRAMC SDRAMC 1 2 SDCKE SDCS RAS CAS SDWE SDA10 A0 - A9, A11 - A13 BA0/BA1 DQM0 - DQM3 D0 - D15 Read D0 - D15 to Write 32072AS–AVR32–03/09 SDRAMC ...
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JTAG Timings 10.10.1 JTAG Interface Signals Table 10-25. JTAG Interface Timing specification Symbol Parameter JTAG TCK Low Half-period 0 JTAG TCK High Half-period 1 JTAG TCK Period 2 JTAG TDI, TMS Setup before TCK High 3 JTAG TDI, TMS ...
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Figure 10-5. JTAG Interface Signals TCK TMS/TDI TDO Device Inputs Device Outputs 10.11 SPI Characteristics Figure 10-6. SPI Master mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1) SPCK MISO MOSI 32072AS–AVR32–03/09 JTAG 2 JTAG 0 JTAG JTAG ...
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Figure 10-7. SPI Master mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0) SPCK MISO MOSI Figure 10-8. SPI Slave mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0) SPCK MISO MOSI Figure 10-9. SPI Slave mode with (CPOL = ...
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Table 10-26. SPI Timings Symbol Parameter SPI MISO Setup time before SPCK rises (master) 0 SPI MISO Hold time after SPCK rises (master) 1 SPI SPCK rising to MOSI Delay (master) 2 SPI MISO Setup time before SPCK falls (master) ...
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Table 10-28. Ethernet MAC MII Specific Signals Symbol Parameter EMAC Hold for ERX from ERXCK 12 EMAC Setup for ERXER from ERXCK 13 EMAC Hold for ERXER from ERXCK 14 EMAC Setup for ERXDV from ERXCK 15 EMAC Hold for ...
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Table 10-29. Ethernet MAC RMII Specific Signals Symbol EMAC EMAC EMAC EMAC EMAC EMAC EMAC EMAC Figure 10-11. Ethernet MAC RMII Mode EREFCK ETXEN ETX[1:0] ERX[1:0] ERXER ECRSDV 10.13 Flash Characteristics The following table gives the device maximum operating frequency ...
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Mechanical Characteristics 11.1 Thermal Considerations 11.1.1 Thermal Data Table 11-1 Table 11-1. Symbol θ JA θ JC θ JA θ JC 11.1.2 Junction Temperature The average chip-junction temperature where: • θ = package thermal ...
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Package Drawings Figure 11-1. TBGA 144 package drawing 32072AS–AVR32–03/09 AT32UC3A3 66 ...
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Figure 11-2. LQFP-144 package drawing Table 11-2. Device and Package Maximum Weight TBD Table 11-3. Package Characteristics Moisture Sensitivity Level Table 11-4. Package Reference JEDEC Drawing Reference JESD97 Classification 32072AS–AVR32–03/09 mg TBD MS-026 E3 AT32UC3A3 67 ...
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Table 11-5. Device and Package Maximum Weight TBD 11.3 Soldering Profile Table 11-6 Table 11-6. Profile Feature Average Ramp-up Rate (217°C to Peak) Preheat Temperature 175°C ±25°C Temperature Maintained Above 217°C Time within 5°C of Actual Peak Temperature Peak Temperature ...
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... AT32UC3A3256-CTUR AT32UC3A3128S AT32UC3A3128S-ALUT AT32UC3A3128S-ALUR AT32UC3A3128S-CTUT AT32UC3A3128S-CTUR AT32UC3A3128 AT32UC3A3128-ALUT AT32UC3A3128-ALUR AT32UC3A3128-CTUT AT32UC3A3128-CTUR AT32UC3A364S AT32UC3A364S-ALUT AT32UC3A364S-ALUR AT32UC3A364S-CTUT AT32UC3A364S-CTUR AT32UC3A364 AT32UC3A364-ALUT AT32UC3A364-ALUR AT32UC3A364-CTUT AT32UC3A364-CTUR 32072AS–AVR32–03/09 Package Conditioning 144 lead LQFP Tray 144 lead LQFP Reels 144 balls TBGA Tray 144 balls TBGA ...
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Errata 13.1 Rev. E 13.1.1 Processor and Architecture 1. LDM instruction with PC in the register list and without ++ increments Rp For LDM with PC in the register list: the instruction behaves as if the ++ field is ...
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When using the STCOND instruction, clear SREG[L] in the stacked value of SR before returning from interrupts with RETE. 3. Exceptions when system stack is protected by MPU RETS behaves incorrectly when MPU is enabled and MPU is configured so ...
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Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 14.1 Rev. A – 03/09 1. 32072AS–AVR32–03/09 Initial revision. ...
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Table of Contents Features ..................................................................................................... 1 1 Description ............................................................................................... 3 2 Blockdiagram ........................................................................................... 4 2.1Processor and Architecture .......................................................................................5 3 Signals Description .................................................................................. 6 4 Package and Pinout ............................................................................... 11 4.1Package ...................................................................................................................11 4.2Peripheral Multiplexing on I/O lines .........................................................................13 4.3Signal Descriptions ..................................................................................................17 ...
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Electrical Characteristics ...................................................................... 44 10.1Absolute Maximum Ratings* .................................................................................44 10.2DC Characteristics .................................................................................................44 10.3Regulator characteristics .......................................................................................46 10.4Power Consumption ..............................................................................................46 10.5Clock Characteristics .............................................................................................48 10.6Crystal Oscillator Characteristis ............................................................................49 10.7ADC Characteristics ..............................................................................................51 10.8USB Transceiver Characteristics ...........................................................................52 10.9EBI Timings ...........................................................................................................53 10.10JTAG Timings ......................................................................................................59 10.11SPI Characteristics ...
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