AT32UC3B0512-A2UT Atmel, AT32UC3B0512-A2UT Datasheet - Page 471

• Manufacturer Part Number: AT32UC3B0512-A2UT
• Description: IC MCU AVR32 512K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-A2UT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Controller Family/series: AT32UC3B
• No. Of I/o's: 44
• Ram Memory Size: 96KB
• Cpu Speed: 60MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.8.3.16
Register Name:
Access Type:
Offset:
Reset Value:
• RSTDT: Reset Data Toggle
• PFREEZE: Pipe Freeze
• PDISHDMA: Pipe Interrupts Disable HDMA Request Enable
• FIFOCON: FIFO Control
• NBUSYBKE: Number of Busy Banks Interrupt Enable
• SHORTPACKETIE: Short Packet Interrupt Enable
32059K–03/2011
PACKETIE
SHORT
31
23
15
7
-
-
-
This bit is set when the RSTDTS bit is written to one. This will reset the Data Toggle to its initial value for the current Pipe.
This bit is cleared when proceed.
This bit is set when the PFREEZES bit is written to one or when the pipe is not configured or when a STALL handshake has
been received on this Pipe or when an error occurs on the Pipe (PERR is one) or when (INRQ+1) In requests have been
processed or when after a Pipe reset (UPRST.PRSTn rising) or a Pipe Enable (UPRST.PEN rising). This will Freeze the Pipe
requests generation.
This bit is cleared when the PFREEZEC bit is written to one. This will enable the Pipe request generation.
See the UECONn.EPDISHDMA bit description.
For OUT and SETUP Pipe:
This bit is set when the current bank is free, at the same time than TXOUTI or TXSTPI.
This bit is cleared when the FIFOCONC bit is written to one. This will send the FIFO data and switch the bank.
For IN Pipe:
This bit is set when a new IN message is stored in the current bank, at the same time than RXINI.
This bit is cleared when the FIFOCONC bit is written to one. This will free the current bank and switch to the next bank.
This bit is set when the NBUSYBKES bit is written to one.This will enable the Transmitted IN Data interrupt (NBUSYBKE).
This bit is cleared when the NBUSYBKEC bit is written to one. This will disable the Transmitted IN Data interrupt (NBUSYBKE).
This bit is set when the SHORTPACKETES bit is written to one. This will enable the Transmitted IN Data IT (SHORTPACKETIE).
This bit is cleared when the SHORTPACKETEC bit is written to one. This will disable the Transmitted IN Data IT
(SHORTPACKETE).
Pipe n Control Register
RXSTALLDE/
CRCERRE
FIFOCON
30
22
14
6
-
-
UPCONn, n in [0..6]
Read-Only
0x05C0 + (n * 0x04)
0x00000000
OVERFIE
29
21
13
5
-
-
-
NBUSYBKE
NAKEDE
28
20
12
4
-
-
PERRE
27
19
11
3
-
-
-
UNDERFIE
TXSTPE/
RSTDT
26
18
10
2
-
-
PFREEZE
TXOUTE
25
17
9
1
-
-
AT32UC3B
PDISHDMA
RXINE
24
16
8
0
-
-
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