ATSAM3S1BA-MU Atmel, ATSAM3S1BA-MU Datasheet - Page 47

• Manufacturer Part Number: ATSAM3S1BA-MU
• Description: IC MCU 32BIT 64KB FLASH 64QFN
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-MU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

12. Embedded Peripherals Overview
12.1
12.2
12.3
6500CS–ATARM–24-Jan-11
Serial Peripheral Interface (SPI)
Two Wire Interface (TWI)
Universal Asynchronous Receiver Transceiver (UART)
• Supports communication with serial external devices
• Master or slave serial peripheral bus interface
• Very fast transfers supported
• Master, Multi-Master and Slave Mode Operation
• Compatibility with Atmel two-wire interface, serial memory and I
• One, two or three bytes for slave address
• Sequential read/write operations
• Bit Rate: Up to 400 kbit/s
• General Call Supported in Slave Mode
• Connecting to PDC channel capabilities optimizes data transfers in Master Mode only
• Two-pin UART
– Four chip selects with external decoder support allow communication with up to 15
– Serial memories, such as DataFlash and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
– External co-processors
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays between consecutive transfers and between clock
– Programmable delay between consecutive transfers
– Selectable mode fault detection
– Transfers with baud rates up to MCK
– The chip select line may be left active to speed up transfers on the same device
– One channel for the receiver, one channel for the transmitter
– Next buffer support
– Independent receiver and transmitter with a common programmable Baud Rate
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
– Support for two PDC channels with connection to receiver and transmitter
peripherals
Sensors
and data per chip select
Generator
SAM3S Summary
2
C compatible devices
47