AT89C51CC01CA-RLTUM Atmel, AT89C51CC01CA-RLTUM Datasheet - Page 29

• Manufacturer Part Number: AT89C51CC01CA-RLTUM
• Description: IC 8051 MCU 32K FLASH 44-VQFP
• Manufacturer: Atmel
• Series: AT89C CANr

Specifications of AT89C51CC01CA-RLTUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1280 B
• Interface Type: UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: CANADAPT28
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4129N–CAN–03/08
Reset Value = X00X 1100b
Not bit addressable
Table 20. AUXR1 Register
AUXR1 (S:A2h)
Auxiliary Control Register 1
Reset Value = XXXX 00X0b
Note:
Number
Number
Bit
Bit
7-6
7
5
4
3
2
1
0
-
1
0
1. ENBOOT is initialized with the invert BLJB at reset. See In-System Programming
section.
Mnemonic Description
Mnemonic Description
ENBOOT
EXTRAM
GF3
DPS
Bit
Bit
A0
6
-
0
-
-
-
(1)
Internal/External RAM (00h - FFh)
access using MOVX @ Ri/@ DPTR
0 - Internal XRAM access using MOVX @ Ri/@ DPTR.
1 - External data memory access.
Disable/Enable ALE)
0 - ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2
mode is used)
1 - ALE is active only during a MOVX or MOVC instruction.
Reserved
The value read from these bits is indeterminate. Do not set these bits.
Enable Boot Flash
Set this bit for map the boot Flash between F800h -FFFFh
Clear this bit for disable boot Flash.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
General-purpose Flag 3
Always Zero
This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3
flag.
Reserved for Data Pointer Extension.
Data Pointer Select Bit
Set to select second dual data pointer: DPTR1.
Clear to select first dual data pointer: DPTR0.
ENBOOT
5
4
-
GF3
3
2
0
1
-
DPS
0
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