AT32UC3A3256-CTUR Atmel, AT32UC3A3256-CTUR Datasheet - Page 87

• Manufacturer Part Number: AT32UC3A3256-CTUR
• Description: IC MCU 256KB FLASH 144TBGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A3256-CTUR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-TBGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, I2S, JTAG, SPI, USART
• Maximum Clock Frequency: 66 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 4
• Operating Supply Voltage: - 0.3 V to + 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

13.3.8
13.3.9
32072C–AVR32–2010/03
PDCA
AES
2. USART - RTS output signal does not function properly in hardware handshaking
3. USART in ISO7816 mode Only in T1: RX impossible after any TX
1. PCONTROL.CHxRES is nonfunctional
1. URAD (Unspecified Register Access Detection Status) does not detect read accesses
mode
The RTS signal is not generated properly when the USART receives data in hardware hand-
shaking mode. When the Peripheral DMA receive buffer becomes full, the RTS output
should go high, but it will stay low.
Fix/Workaround
Do not use the hardware handshaking mode of the USART. If it is necessary to drive the
RTS output high when the Peripheral DMA receive buffer becomes full, use the normal
mode of the USART. Configure the Peripheral DMA Controller to signal an interrupt when
the receive buffer is full. In the interrupt handler code, write a one to the RTSDIS bit in the
USART Control Register (CR). This will drive the RTS output high. After the next DMA trans-
fer is started and a receive buffer is available, write a one to the RTSEN bit in the USART
CR so that RTS will be driven low.
Fix/workaround
Reset the TX transceiver by setting RSTTX field in CR register, then configure MR register
and CR register.
PCONTROL.CHxRES is nonfunctional. Counters are reset at power-on, and cannot be
reset by software.
Fix/Workaround
Software needs to keep history of performance counters.
to the write-only KEYW[5..8]R registers
Fix/Workaround
None.
AT32UC3A3/A4
87