ATSAM3S4AA-AU Atmel, ATSAM3S4AA-AU Datasheet - Page 48

• Manufacturer Part Number: ATSAM3S4AA-AU
• Description: IC MCU 32BIT 256KB FLASH 48LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4AA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 8x10/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 34
• Ram Memory Size: 48KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Package: 48LQFP
• Device Core: ARM Cortex M3
• Family Name: AT91
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 34
• Interface Type: I2C/I2S/SPI/UART/USART/USB
• On-chip Adc: 9-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.4
12.5
12.6
48
Universal Synchronous Asynchronous Receiver Transceiver (USART)
Synchronous Serial Controller (SSC)
Timer Counter (TC)
SAM3S Summary
• Programmable Baud Rate Generator with Fractional Baud rate support
• 5- to 9-bit full-duplex synchronous or asynchronous serial communications
• RS485 with driver control signal
• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
• SPI Mode
• IrDA modulation and demodulation
• Test Modes
• Provides serial synchronous communication links used in audio and telecom applications
• Contains an independent receiver and transmitter and a common clock divider
• Offers configurable frame sync and data length
• Receiver and transmitter can be programmed to start automatically or on detection of
• Receiver and transmitter include a data signal, a clock signal and a frame synchronization
• Six 16-bit Timer Counter Channels
• Wide range of functions including:
(with CODECs in Master or Slave Modes, I
different event on the frame sync signal
signal
– 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
– Parity generation and error detection
– Framing error detection, overrun error detection
– MSB- or LSB-first
– Optional break generation and detection
– By 8 or by-16 over-sampling receiver frequency
– Hardware handshaking RTS-CTS
– Receiver time-out and transmitter timeguard
– Optional Multi-drop Mode with address generation and detection
– Optional Manchester Encoding
– Full modem line support on USART1 (DCD-DSR-DTR-RI)
– NACK handling, error counter with repetition and iteration limit
– Master or Slave
– Serial Clock programmable Phase and Polarity
– SPI Serial Clock (SCK) Frequency up to MCK/4
– Communication at up to 115.2 Kbps
– Remote Loopback, Local Loopback, Automatic Echo
– Frequency Measurement
– Event Counting
2
S, TDM Buses, Magnetic Card Reader)
6500CS–ATARM–24-Jan-11