AT91SAM9260B-CU Atmel, AT91SAM9260B-CU Datasheet
AT91SAM9260B-CU
Specifications of AT91SAM9260B-CU
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AT91SAM9260B-CU Summary of contents
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Features ® • 180 MHz ARM926EJ-S™ ARM Thumb – 8 KBytes Data Cache, 8 KBytes Instruction Cache, MMU • Memories – 32-bit External Bus Interface supporting 4-bank SDRAM/LPSDR, Static Memories, CompactFlash, SLC NAND Flash with ECC – Two 4-kbyte internal ...
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Description The AT91SAM9260 is based on the integration of an ARM926EJ-S processor with fast ROM and RAM memories and a wide range of peripherals. The AT91SAM9260 embeds an Ethernet MAC, one USB Device Port, and a USB Host control- ...
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Figure 2-1. AT91SAM9260 Block Diagram 6221JS–ATARM–17-Jul-09 Filter AT91SAM9260 3 ...
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Signal Description Table 3-1. Signal Description List Signal Name Function VDDIOM EBI I/O Lines Power Supply VDDIOP0 Peripherals I/O Lines Power Supply VDDIOP1 Peripherals I/O Lines Power Supply VDDBU Backup I/O Lines Power Supply VDDANA Analog Power Supply VDDPLL ...
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Table 3-1. Signal Description List (Continued) Signal Name Function NRST Microcontroller Reset TST Test Mode Select BMS Boot Mode Select DRXD Debug Receive Data DTXD Debug Transmit Data IRQ0 - IRQ2 External Interrupt Inputs FIQ Fast Interrupt Input PA0 - ...
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Table 3-1. Signal Description List (Continued) Signal Name Function NANDCS NAND Flash Chip Select NANDOE NAND Flash Output Enable NANDWE NAND Flash Write Enable NANDALE NAND Flash Address Latch Enable NANDCLE NAND Flash Command Latch Enable SDCK SDRAM Clock SDCKE ...
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Table 3-1. Signal Description List (Continued) Signal Name Function TCLKx TC Channel x External Clock Input TIOAx TC Channel x I/O Line A TIOBx TC Channel x I/O Line B SPIx_MISO Master In Slave Out SPIx_MOSI Master Out Slave In ...
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Table 3-1. Signal Description List (Continued) Signal Name Function ISI_D0-ISI_D11 Image Sensor Data ISI_MCK Image Sensor Reference Clock ISI_HSYNC Image Sensor Horizontal Synchro ISI_VSYNC Image Sensor Vertical Synchro ISI_PCK Image Sensor Data clock AD0-AD3 Analog Inputs ADVREF Analog Positive Reference ...
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Package and Pinout The AT91SAM9260 is available in two packages: • 208-pin PQFP Green package (0.5mm pitch) • 217-ball LFBGA Green package (0.8 mm ball pitch) 4.1 208-pin PQFP Package Outline Figure 4-1 A detailed mechanical description is given ...
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PQFP Pinout Table 4-1. Pinout for 208-pin PQFP Package Pin Signal Name Pin 1 PA24 53 2 PA25 54 3 PA26 55 4 PA27 56 5 VDDIOP0 57 6 GND 58 7 PA28 59 8 PA29 60 9 ...
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Table 4-1. Pinout for 208-pin PQFP Package (Continued) Pin Signal Name Pin 49 SHDN 101 50 HDMA 102 51 HDPA 103 52 VDDIOP0 104 4.3 217-ball LFBGA Package Outline Figure 4-2 A detailed mechanical description is given in the section ...
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LFBGA Pinout Table 4-2. Pinout for 217-ball LFBGA Package Pin Signal Name Pin A1 CFIOW/NBS3/NWR3 D5 A2 NBS0/ NWR2/NBS2/ A11 D10 A7 A13 D11 A8 BA0/A16 D12 A9 ...
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Table 4-2. Pinout for 217-ball LFBGA Package (Continued) Pin Signal Name C16 VDDIOP0 C17 SHDN RAS Power Considerations 5.1 Power Supplies The AT91SAM9260 has several types of power supply pins: • VDDCORE ...
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Programmable I/O Lines Power Supplies The power supplies pins VDDIOM accept two voltage ranges. This allows the device to reach its maximum speed either out of 1.8V or 3.3V external memories. The target maximum speed is 100 MHz on ...
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PIO Controllers All the I/O lines managed by the PIO Controllers integrate a programmable pull-up resistor. Refer to the section on DC Characteristics in “AT91SAM9260 Electrical Characteristics” for more information. Programming of this pull-up resistor is performed independently for ...
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DSP Instruction Extensions • 5-Stage Pipeline Architecture: – Instruction Fetch (F) – Instruction Decode (D) – Execute (E) – Data Memory (M) – Register Write (W) • 8-Kbyte Data Cache, 8-Kbyte Instruction Cache – Virtually-addressed 4-way Associative Cache – ...
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Boot Mode Select – Non-volatile Boot Memory can be internal or external – Selection is made by BMS pin sampled at reset • Remap Command – Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory ...
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Table 7- External Bus Interface 4 7.3 Peripheral DMA Controller • Acting as one Matrix Master • Allows data transfers from/to peripheral to/from any memory space without any intervention of the processor. • Next Pointer Support, forbids ...
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SPI0 Receive Channel – SSC Receive Channel – MCI Transmit/Receive Channel 7.4 Debug and Test Features • ARM926 Real-time In-circuit Emulator – Two real-time Watchpoint Units – Two Independent Registers: Debug Control Register and Debug Status Register – Test ...
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Memories Figure 8-1. AT91SAM9260 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256M Bytes 0x0FFF FFFF 0x1000 0000 EBI 256M Bytes Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI 256M Bytes Chip Select 1/ SDRAMC 0x2FFF FFFF 0x3000 ...
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A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High Performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4G bytes of address space ...
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The AT91SAM9260 matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose. If BMS is detected at 1, ...
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ECC Controller • Additional logic for NAND Flash • Full 32-bit External Data Bus • 26-bit Address Bus (up to 64MBytes linear) • chip selects, Configurable Assignment: – Static Memory Controller on NCS0 – ...
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Error detection – Refresh Error Interrupt • SDRAM Power-up Initialization by software • CAS Latency and 3 supported • Auto Precharge Command not used 8.2.4 Error Corrected Code Controller • Tracking the accesses to a NAND ...
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System Controller The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds the registers that configure ...
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Block Diagram Figure 9-1. AT91SAM9260 System Controller Block Diagram irq0-irq2 periph_irq[2..24] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset dbgu_rxd periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset SHDN WKUP RC OSC OSC_SEL SLOW XIN32 CLOCK OSC XOUT32 XIN ...
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Reset Controller • Based on two Power-on-reset cells – One on VDDBU and one on VDDCORE • Status of the last reset – Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software • Controls the internal resets and ...
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Figure 9-2. 9.5 Power Management Controller • Provides: – the Processor Clock PCK – the Master Clock MCK, in particular to the Matrix and the memory interfaces – the USB Device Clock UDPCK – independent peripheral clocks, typically at the ...
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Figure 9-3. 9.6 Periodic Interval Timer • Includes a 20-bit Periodic Counter, with less than 1 µs accuracy • Includes a 12-bit Interval Overlay Counter • Real Time OS or Linux 9.7 Watchdog Timer • 16-bit key-protected only-once-Programmable Counter • ...
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... Two-pin UART – Debug Communication Channel (DCC) support • Two-pin UART – Implemented features are 100% compatible with the standard Atmel – Independent receiver and transmitter with a common programmable Baud Rate – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – ...
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Peripherals 10.1 User Interface The peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory map ...
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Table 10-1. Peripheral Note: Setting AIC, SYSC, UHP and IRQ0-2 bits in the clock set/clear registers of the PMC has no effect. 10.2.1 Peripheral Interrupts and Clock Control 10.2.1.1 System Interrupt The System Interrupt in Source ...
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PIO Controller A Multiplexing Table 10-2. Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A PA0 SPI0_MISO PA1 SPI0_MOSI PA2 SPI0_SPCK PA3 SPI0_NPCS0 PA4 RTS2 PA5 CTS2 PA6 MCDA0 PA7 MCCDA PA8 MCCK PA9 MCDA1 PA10 ...
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PIO Controller B Multiplexing Table 10-3. Multiplexing on PIO Controller B PIO Controller B I/O Line Peripheral A Peripheral B PB0 SPI1_MISO TIOA3 PB1 SPI1_MOSI TIOB3 PB2 SPI1_SPCK TIOA4 PB3 SPI1_NPCS0 TIOA5 PB4 TXD0 PB5 RXD0 PB6 TXD1 TCLK1 ...
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PIO Controller C Multiplexing Table 10-4. Multiplexing on PIO Controller C PIO Controller C I/O Line Peripheral A PC0 PC1 (1) PC2 (1) PC3 PC4 A23 PC5 A24 PC6 TIOB2 PC7 TIOB1 PC8 NCS4/CFCS0 PC9 NCS5/CFCS1 PC10 A25/CFRNW PC11 ...
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Embedded Peripherals 10.4.1 Serial Peripheral Interface • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with – Serial memories, such as DataFlash and 3-wire EEPROMs – Serial peripherals, ...
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Communication 115.2 Kbps • Test Modes – Remote Loopback, Local Loopback, Automatic Echo The USART contains features allowing management of the Modem Signals DTR, DSR, DCD and RI. In the AT91SAM9260, only the USART0 implements these ...
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Compatibility with SD Memory Card Specification Version 1.1 • Compatibility with SDIO Specification Version V1.0. • Card clock rate up to Master Clock divided by 2 • Embedded power management to slow down clock rate when not used • ...
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Support physical layer management through MDIO interface 10.4.10 Image Sensor Interface • ITU-R BT. 601/656 8-bit mode external interface support • Support for ITU-R BT.656-4 SAV and EAV synchronization • Vertical and horizontal resolutions up to 2048 x 2048 ...
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AT91SAM9260 Mechanical Characteristics 11.1 Package Drawings Figure 11-1. 217-ball LFBGA Package Drawing Table 11-1. Soldering Informations Ball Land Soldering Mask Opening Table 11-2. Device and 217-ball LFBGA Package Maximum Weight 450 Table 11-3. 217-ball LFBGA Package Characteristics Moisture Sensitivity ...
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Figure 11-2. 208-lead PQFP Package Drawing Table 11-5. Device and 208-lead PQFP Package Maximum Weight 5.5 Table 11-6. 208-lead PQFP Package Characteristics Moisture Sensitivity Level Table 11-7. Package Reference JEDEC Drawing Reference JESD97 Classification 6221JS–ATARM–17-Jul-09 AT91SAM9260 g 3 MS-022 e3 ...
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Soldering Profile Table 11-8 Table 11-8. Profile Feature Average Ramp-up Rate (217°C to Peak) Preheat Temperature 175°C ±25°C Temperature Maintained Above 217°C Time within 5° Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25° ...
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... AT91SAM9260 Ordering Information Table 12-1. AT91SAM9260 Ordering Information Marketing Revision Level A Marketing Revision Level B Ordering Code AT91SAM9260-QU AT91SAM9260-CU 6221JS–ATARM–17-Jul-09 Ordering Code Package AT91SAM9260B-QU PQFP208 AT91SAM9260B-CU BGA217 AT91SAM9260 Temperature Operating Package Type Range Green Industrial -40°C to 85°C Green 43 ...
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Revision History Table 13-1. Revision History - current version appears first Revision Comments Line added to Note edited after ‘Manchester Encoding/Decoding’ removed from 6221JS Synchronous/Asynchronous Receiver Transmitters (USART)” on page 2 Section 6.6 ”Shutdown Logic Pins” on page 15 ...
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Table 13-1. Revision History - current version appears first Revision Comments Updated information on programmable pull-up resistor in page 15 . Section 6.7 ”Slow Clock Selection” on page 15 Updated 6221ES Table 10-1, “AT91SAM9260 Peripheral Identifiers,” on page 31 In ...
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AT91SAM9260 46 6221JS–ATARM–17-Jul-09 ...
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