ADUC7128BCPZ126 Analog Devices Inc, ADUC7128BCPZ126 Datasheet - Page 79

• Manufacturer Part Number: ADUC7128BCPZ126
• Description: IC DAS MCU ARM7 ADC/DDS 64-LFCSP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7128BCPZ126

• Core Size: 16/32-Bit
• Program Memory Size: 126KB (126K x 8)
• Core Processor: ARM7
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: PLA, POR, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 28
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LFCSP
• Controller Family/series: (ARM7) ADUC
• No. Of I/o's: 40
• Ram Memory Size: 8KB
• Cpu Speed: 41.78MHz
• No. Of Timers: 5
• No. Of Pwm Channels: 6
• Package: 64LFCSP EP
• Device Core: ARM7TDMI
• Family Name: ADuC7xxx
• Maximum Speed: 41.78 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 40
• Interface Type: I2C/SPI/UART
• On-chip Adc: 14-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC7128QSPZ - KIT DEV FOR ADUC7128
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TIMER3—WATCHDOG TIMER
Timer3 has two modes of operation: normal mode and
watchdog mode. The watchdog timer is used to recover from an
illegal software state. Once enabled, it requires periodic
servicing to prevent it from forcing a reset of the processor.
Timer3 reloads the value from T3LD either when Timer3
overflows or immediately after T3ICLR is written.
Normal Mode
The Timer3 in normal mode is identical to Timer0 in 16-bit
mode of operation, except for the clock source. The clock source
is the 32.768 kHz oscillator and can be scaled by a factor of 1,
16, or 256. Timer3 also features a capture facility that allows
capture of the current timer value if the Timer2 interrupt is
enabled via IRQEN[5].
Watchdog Mode
Watchdog mode is entered by setting T3CON[5]. Timer3 decre-
ments from the timeout value present in the T3LD register to 0.
The maximum timeout is 512 seconds, using the maximum
prescalar/256 and full scale in T3LD.
User software should only configure a minimum timeout
period of 30 ms. This is to avoid any conflict with Flash/EE
memory page erase cycles, which require 20 ms to complete
a single page erase cycle and kernel execution.
If T3VAL reaches 0, a reset or an interrupt occurs, depending
on T3CON[1]. To avoid a reset or an interrupt event, any value
can be written to T3ICLR before T3VAL reaches 0. This reloads
the counter with T3LD and begins a new timeout period.
Once watchdog mode is entered, T3LD and T3CON are write
protected. These two registers cannot be modified until a
power-on reset event resets the watchdog timer. After any other
reset event, the watchdog timer continues to count. The
watchdog timer should be configured in the initial lines of user
code to avoid an infinite loop of watchdog resets.
LOW POWER
32.768kHz
Figure 58. Timer3 Block Diagram
1, 16, OR 256
PRESCALER
TIMER3 VALUE
16-BIT LOAD
UP/DOWN
COUNTER
16-BIT
WATCHDOG
RESET
TIMER3IRQ
Rev. 0 | Page 79 of 92
Timer3 is automatically halted during JTAG debug access and
only recommences counting once JTAG has relinquished control
of the ARM7 core. By default, Timer3 continues to count during
power-down. This can be disabled by setting Bit 0 in T3CON. It is
recommended that the default value is used, that is, the watchdog
timer continues to count during power-down.
Timer3 Interface
The Timer3 interface consists of four MMRs, as shown in Table 114.
Table 114. Timer3 Interface MMRs
Name
T3CON
T3LD
T3VAL
T3ICLR
Timer3 Load Register
Name
T3LD
This 16-bit MMR holds the Timer3 reload value.
Timer3 Value Register
Name
T3VAL
This 16-bit, read-only MMR holds the current Timer3 count value.
Timer3 Clear Register
Name
T3ICLR
This 8-bit, write-only MMR is written (with any value) by user
code to refresh (reload) Timer3 in watchdog mode to prevent a
watchdog timer reset event.
Timer3 Control Register
Name
T3CON
The 16-bit MMR configures the mode of operation of Timer3.
as described in detail in Table 115.
Description
The configuration MMR (see Table 115).
A 16-bit register (Bit 0 to Bit15). Holds 16-bit
unsigned integers.
A 16-bit register (Bit 0 to Bit 15). Holds 16-bit
unsigned integers. This register is read only.
An 8-bit register. Writing any value to this register
clears the Timer3 interrupt in normal mode or resets
a new timeout period in watchdog mode.
Address
0xFFFF0360
Address
0xFFFF0364
Address
0xFFFF036C
Address
0xFFFF0368
ADuC7128/ADuC7129
Default Value
0x03D7
Default Value
0x03D7
Default Value
0x00
Default Value
0x00
Access
R/W
Access
R
Access
W
Access
R/W
once
only