STM8S103K3T3C STMicroelectronics, STM8S103K3T3C Datasheet - Page 17
STM8S103K3T3C
Manufacturer Part Number
STM8S103K3T3C
Description
MCU 8BIT 8K FLASH 32LQFP
Manufacturer
STMicroelectronics
Series
STM8Sr
Datasheet
1.STM8S103F2P6TR.pdf
(113 pages)
Specifications of STM8S103K3T3C
Core Processor
STM8
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
28
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
640 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.95 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
32-LQFP
Processor Series
STM8S10x
Core
STM8
3rd Party Development Tools
EWSTM8
Development Tools By Supplier
STM8/128-MCKIT, STM8S-DISCOVERY, ST-LINK, STICE-SYS001, STX-RLINK
Featured Product
STM32 Cortex-M3 Companion Products
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM8S103K3T3C
Manufacturer:
STMicroelectronics
Quantity:
10 000
STM8S103K3 STM8S103F3 STM8S103F2
4.14
4.14.1
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Communication interfaces
The following communication interfaces are implemented:
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UART1
Main features
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Asynchronous communication (UART mode)
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Synchronous communication
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Analog watchdog capability with programmable upper and lower thresholds
Analog watchdog interrupt
External trigger input
Trigger from TIM1 TRGO
End of conversion (EOC) interrupt
UART1: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA
mode, single wire mode, LIN2.1 master capability
SPI : Full and half-duplex, 8 Mbit/s
I²C: Up to 400 Kbit/s
One Mbit/s full duplex SCI
SPI emulation
High precision baud rate generator
Smartcard emulation
IrDA SIR encoder decoder
LIN master mode
Single wire half duplex mode
Full duplex communication - NRZ standard format (mark/space)
Programmable transmit and receive baud rates up to 1 Mbit/s (f
following any standard baud rate regardless of the input frequency
Separate enable bits for transmitter and receiver
Two receiver wakeup modes:
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Transmission error detection with interrupt generation
Parity control
Full duplex synchronous transfers
SPI master operation
8-bit data communication
Maximum speed: 1 Mbit/s at 16 MHz (f
Address bit (MSB)
Idle line (interrupt)
DocID15441 Rev 6
CPU
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CPU
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Product overview
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