STR751FR0H6 STMicroelectronics, STR751FR0H6 Datasheet - Page 49

• Manufacturer Part Number: STR751FR0H6
• Description: MCU 32BIT 64KB FLASH 64LFBGA
• Manufacturer: STMicroelectronics
• Series: STR7r

Specifications of STR751FR0H6

• Core Processor: ARM7
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, SPI, SSI, SSP, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LFBGA
• For Use With: MCBSTR750UME - BOARD EVAL MCBSTR750 + ULINK-MEMCBSTR750U - BOARD EVAL MCBSTR750 + ULINK2497-5754 - KIT STARTER IAR STR750497-5753 - KIT STARTER KEIL FOR STR7/STR9497-5752 - KIT STARTER IAR FOR STR7/STR9497-5748 - BOARD EVALUATION FOR STR750XF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

STR750Fxx STR751Fxx STR752Fxx STR755Fxx
PLL characteristics
Subject to general operating conditions for V
Table 24.
1. Data based on product characterisation, not tested in production.
2. Refer to jitter terminology in
3. The jitter specification holds true only up to 50mV (peak-to-peak) noise on V
4. The PLL parameters (MX1, MX0, PRESC1, PRESC2) must respect the constraints described
Internal RC oscillators (FREEOSC & LPOSC)
Subject to general operating conditions for V
Table 25.
f
f
Δt
Δt
Δt
CK_FREEOSC
CK_LPOSC
JITTER1
JITTER2
JITTER3
f
Jitter will increase if the noise is more than 50mV. In addition, it assumes that the input clock has no jitter.
characteristics on page
Symbol
Symbol
PLL_OUT
f
PLL_IN
t
f
LOCK
VCO
(2)(3)
(2)(3)
(2)(3)
PLL characteristics
Internal RC oscillators (FREEOSC & LPOSC)
FREEOSC Oscillator Frequency
LPOSC Oscillator Frequency
PLL input clock
PLL input clock duty cycle
PLL multiplier output clock
VCO frequency range
PLL lock time
Single period jitter (+/-3Σ peak
to peak)
Long term jitter (+/-3Σ peak to
peak)
Cycle to cycle jitter (+/-3Σ peak
to peak)
47.
Parameter
Parameter
: PLL characteristics on page 47
f
When PLL
operates (locked)
f
V
f
V
f
V
DD_IO
DD_IO
PLL_IN
PLL_IN
PLL_IN
PLL_IN
Test Conditions
DD_IO
DD_IO
DD_IO
Conditions
, and T
, and T
x 24
= 4 MHz
= 4 MHz
= 4 MHz
is stable
is stable
is stable
for details on how jitter is specified.
A
A
.
.
(4)
(4)
(4)
Min
150
3
Min
336
40
DDA_PLL
Typ
300
Electrical parameters
5
Typ
4.0
Value
and V
18
Max
500
Max
+/-250
+/-500
+/-2.5
8
supplies.
165
960
300
in: PLL
60
(1)
MHz
Unit
kHz
MHz
MHz
MHz
Unit
49/84
μs
ps
ns
ps
%