STM32F103VET7 STMicroelectronics, STM32F103VET7 Datasheet

MCU ARM 32BIT 512K FLASH 100LQFP

STM32F103VET7

Manufacturer Part Number
STM32F103VET7
Description
MCU ARM 32BIT 512K FLASH 100LQFP
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet

Specifications of STM32F103VET7

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
Peripherals
DMA, Motor Control PWM, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
80
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-LQFP
Processor Series
STM32F103x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
CAN, I2C, SPI, USART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
80
Number Of Timers
8
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
3 (12 bit, 16 Channel)
On-chip Dac
2 (12 bit, 2 Channel)
Featured Product
STM32 Cortex-M3 Companion Products
Eeprom Size
-
A/d Bit Size
12 bit
A/d Channels Available
16
Height
1.4 mm
Length
14 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2 V
Width
14 mm
For Use With
497-10048 - BOARD EVAL ACCELEROMETER497-10030 - STARTER KIT FOR STM32KSDKSTM32-PL - KIT IAR KICKSTART STM32 CORTEXM3497-8512 - KIT STARTER FOR STM32F10XE MCU497-8511 - KIT STARTER FOR STM32 512K FLASH497-8505 - KIT STARTER FOR STM32F10XE MCU497-6438 - BOARD EVALUTION FOR STM32 512K497-6289 - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U - BOARD EVAL MCBSTM32 + ULINK2MCBSTM32 - BOARD EVAL FOR STM STM32X SER497-6053 - KIT STARTER FOR STM32497-6052 - KIT STARTER FOR STM32497-6050 - KIT STARTER FOR STM32497-6049 - KIT EVALUATION LOW COST STM32497-6048 - BOARD EVALUATION FOR STM32497-6047 - KIT DEVELOPMENT FOR STM32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STM32F103VET7
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
STM32F103VET7TR
Manufacturer:
ST
0
512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces
Features
September 2009
High-density performance line ARM-based 32-bit MCU with 256 to
Core: ARM 32-bit Cortex™-M3 CPU
– 72 MHz maximum frequency,
– Single-cycle multiplication and hardware
Memories
– 256 to 512 Kbytes of Flash memory
– up to 64 Kbytes of SRAM
– Flexible static memory controller with 4
– LCD parallel interface, 8080/6800 modes
Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC with calibration
– 32 kHz oscillator for RTC with calibration
Low power
– Sleep, Stop and Standby modes
– V
3 × 12-bit, 1 µs A/D converters (up to 21
channels)
– Conversion range: 0 to 3.6 V
– Triple-sample and hold capability
– Temperature sensor
2 × 12-bit D/A converters
DMA: 12-channel DMA controller
– Supported peripherals: timers, ADCs, DAC,
Debug mode
– Serial wire debug (SWD) & JTAG interfaces
– Cortex-M3 Embedded Trace Macrocell™
1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 wait state memory
access
division
Chip Select. Supports Compact Flash,
SRAM, PSRAM, NOR and NAND memories
detector (PVD)
SDIO, I
BAT
supply for RTC and backup registers
2
Ss, SPIs, I
2
Cs and USARTs
Doc ID 14611 Rev 7
STM32F103xC STM32F103xD
Table 1.
STM32F103xC
STM32F103xD
STM32F103xE
LQFP100 14 × 14 mm,
LQFP144 20 × 20 mm
LQFP64 10 × 10 mm,
Reference
Up to 112 fast I/O ports
– 51/80/112 I/Os, all mappable on 16
Up to 11 timers
– Up to four 16-bit timers, each with up to 4
– 2 × 16-bit motor control PWM timers with
– 2 × watchdog timers (Independent and
– SysTick timer: a 24-bit downcounter
– 2 × 16-bit basic timers to drive the DAC
Up to 13 communication interfaces
– Up to 2 × I
– Up to 5 USARTs (ISO 7816 interface, LIN,
– Up to 3 SPIs (18 Mbit/s), 2 with I
– CAN interface (2.0B Active)
– USB 2.0 full speed interface
– SDIO interface
CRC calculation unit, 96-bit unique ID
ECOPACK
external interrupt vectors and almost all
5 V-tolerant
IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
dead-time generation and emergency stop
Window)
IrDA capability, modem control)
interface multiplexed
Device summary
®
packages
STM32F103RC STM32F103VC
STM32F103ZC
STM32F103RD STM32F103VD
STM32F103ZD
STM32F103RE STM32F103ZE
STM32F103VE
2
C interfaces (SMBus/PMBus)
STM32F103xE
WLCSP64
Part number
LFBGA100 10 × 10 mm
LFBGA144 10 × 10 mm
2
S
FBGA
www.st.com
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Related parts for STM32F103VET7

STM32F103VET7 Summary of contents

Page 1

High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces Features ■ Core: ARM 32-bit Cortex™-M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait ...

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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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STM32F103xC, STM32F103xD, STM32F103xE 2.3.29 2.3.30 3 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Contents 5.3.20 6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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STM32F103xC, STM32F103xD, STM32F103xE List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of tables Table 45. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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STM32F103xC, STM32F103xD, STM32F103xE List of figures Figure 1. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram . . . 12 Figure 2. Clock tree . . . . . . . . . . . . . . . . ...

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List of figures Figure 39. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F103xC, STM32F103xD and STM32F103xE high-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family, please refer to Section 2.2: Full compatibility throughout the The high-density STM32F103xx datasheet should be read in conjunction with the STM32F10xxx reference manual ...

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Description 2 Description The STM32F103xC, STM32F103xD and STM32F103xE performance line family incorporates the high-performance ARM 72 MHz frequency, high-speed embedded memories (Flash memory up to 512 Kbytes and SRAM Kbytes), and an extensive range of enhanced I/Os ...

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STM32F103xC, STM32F103xD, STM32F103xE 2.1 Device overview Table 2. STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts Peripherals Flash memory in Kbytes SRAM in Kbytes FSMC General-purpose Timers Advanced-control Basic 2 (3) SPI USART Comm USB CAN ...

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Description Figure 1. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram TRACECLK TRACED[0:3] TPIU as AS Trace/trig SW/JTAG NJTRST JTDI JTCK/SWCLK Cortex-M3 CPU JTMS/SWDIO JTDO max : 48/72 MHz NVIC GP DMA1 A[25:0] 7 channels D[15:0] CLK ...

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STM32F103xC, STM32F103xD, STM32F103xE Figure 2. Clock tree 8 MHz HSI RC PLLSRC OSC_OUT 4-16 MHz HSE OSC OSC_IN OSC32_IN LSE OSC 32.768 kHz OSC32_OUT LSI RC 40 kHz Main Clock Output MCO 1. When the HSI is used as a ...

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Description 2.2 Full compatibility throughout the family The STM32F103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low-density devices, the STM32F103x8 and STM32F103xB are ...

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STM32F103xC, STM32F103xD, STM32F103xE 2.3 Overview ® 2.3.1 ARM Cortex™-M3 core with embedded Flash and SRAM The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets ...

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Description 2.3.6 LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel ...

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STM32F103xC, STM32F103xD, STM32F103xE 2.3.10 Boot modes At startup, boot pins are used to select one of three boot options: ● Boot from User Flash ● Boot from System Memory ● Boot from embedded SRAM The boot loader is located in ...

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Description 2.3.14 Low-power modes The STM32F103xC, STM32F103xD and STM32F103xE performance line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ● Sleep mode In Sleep mode, only the CPU ...

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STM32F103xC, STM32F103xD, STM32F103xE periodic interrupt clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of ...

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Description General-purpose timers (TIMx) There are synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5) embedded in the STM32F103xC, STM32F103xD and STM32F103xE performance line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler ...

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STM32F103xC, STM32F103xD, STM32F103xE 2.3.19 Universal synchronous/asynchronous receiver transmitters (USARTs) The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4 and UART5). These five interfaces provide asynchronous ...

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Description 2.3.24 Universal serial bus (USB) The STM32F103xC, STM32F103xD and STM32F103xE performance line embed a USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting ...

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STM32F103xC, STM32F103xD, STM32F103xE This dual digital Interface supports the following features: ● two DAC converters: one for each output channel ● 8-bit or 12-bit monotonic output ● left or right data alignment in 12-bit mode ● synchronized update capability ● ...

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Pinouts and pin descriptions 3 Pinouts and pin descriptions Figure 3. STM32F103xC and STM32F103xE performance line BGA144 ballout PC13- PE3 PE2 A TAMPER-RTC PC14- B PE4 PE5 OSC32_IN PC15 BAT PF0 OSC32_OUT D OSC_IN V ...

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STM32F103xC, STM32F103xD, STM32F103xE Figure 4. STM32F103xC and STM32F103xE performance line BGA100 ballout 1 2 PC14- PC13- A PE2 OSC32_IN TAMPER-RTC PC15 BAT PE3 OSC32_OUT C OSC_IN V SS_5 PE4 D OSC_OUT V DD_5 PE5 E NRST PE6 PC2 ...

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Pinouts and pin descriptions Figure 5. STM32F103xC and STM32F103xE performance line LQFP144 pinout PE2 1 PE3 2 PE4 3 PE5 4 PE6 5 VBAT 6 PC13-TAMPER-RTC 7 PC14-OSC32_IN 8 PC15-OSC32_OUT 9 PF0 10 PF1 11 PF2 12 PF3 13 PF4 ...

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STM32F103xC, STM32F103xD, STM32F103xE Figure 6. STM32F103xC and STM32F103xE performance line LQFP100 pinout VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST VSSA VREF- VREF+ VDDA PA0-WKUP PE2 1 PE3 2 PE4 3 PE5 4 PE6 ...

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Pinouts and pin descriptions Figure 7. STM32F103xC and STM32F103xE performance line LQFP64 pinout PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT 28/123 STM32F103xC, STM32F103xD, STM32F103xE VBAT ...

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STM32F103xC, STM32F103xD, STM32F103xE Figure 8. STM32F103xC and STM32F103xE performance line WLCSP64 ballout, ball side PC14 C PC13 D OSC_IN OSC_OUT E F PC1 BOOT0 PB5 DD_3 SS_3 PC15 PB9 ...

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Pinouts and pin descriptions Table 5. High-density STM32F103xx pin definitions Pins Pin name ...

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STM32F103xC, STM32F103xD, STM32F103xE Table 5. High-density STM32F103xx pin definitions (continued) Pins Pin name ( PA0-WKUP K2 ...

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Pinouts and pin descriptions Table 5. High-density STM32F103xx pin definitions (continued) Pins Pin name ...

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STM32F103xC, STM32F103xD, STM32F103xE Table 5. High-density STM32F103xx pin definitions (continued) Pins Pin name L10 K10 - - 59 81 K10 J10 - - ...

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Pinouts and pin descriptions Table 5. High-density STM32F103xx pin definitions (continued) Pins Pin name A12 A10 105 C11 106 107 108 A11 A9 ...

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... This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 9. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins ...

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Pinouts and pin descriptions Table 6. FSMC pin definition Pins CF PE2 PE3 PE4 PE5 PE6 PF0 A0 PF1 A1 PF2 A2 PF3 A3 PF4 A4 PF5 A5 PF6 NIORD PF7 NREG PF8 NIOWR PF9 CD PF10 INTR PF11 NIOS16 ...

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STM32F103xC, STM32F103xD, STM32F103xE Table 6. FSMC pin definition (continued) Pins CF PD9 D14 PD10 D15 PD11 PD12 PD13 PD14 D0 PD15 D1 PG2 PG3 PG4 PG5 PG6 PG7 PD0 D2 PD1 D3 PD3 PD4 NOE PD5 NWE PD6 NWAIT PD7 ...

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Memory mapping 4 Memory mapping The memory map is shown in Figure 9. Memory map 0xFFFF FFFF 0xE000 0000 0xDFFF FFFF 0xC000 0000 0xBFFF FFFF 0xA000 0000 0x9FFF FFFF 0x8000 0000 0x7FFF FFFF 0x6000 0000 0x5FFF FFFF 0x4000 0000 0x3FFF ...

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STM32F103xC, STM32F103xD, STM32F103xE 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to V 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, ...

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Electrical characteristics 5.1.6 Power supply scheme Figure 12. Power supply scheme 1.8-3.6V 11 × 100 × 4.7 µ µ µF Caution: In Figure 12, the 4.7 µF ...

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STM32F103xC, STM32F103xD, STM32F103xE 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 8: Current characteristics, and damage to the device. These are stress ratings only and functional operation of the device at these conditions is not ...

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Electrical characteristics Table 9. Thermal characteristics Symbol T STG T J 5.3 Operating conditions 5.3.1 General operating conditions Table 10. General operating conditions Symbol f Internal AHB clock frequency HCLK f Internal APB1 clock frequency PCLK1 f Internal APB2 clock ...

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STM32F103xC, STM32F103xD, STM32F103xE 5.3.2 Operating conditions at power-up / power-down The parameters given in temperature condition summarized in Table 11. Operating conditions at power-up / power-down Symbol V rise time rate DD t VDD V fall time rate DD 5.3.3 ...

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Electrical characteristics 5.3.4 Embedded reference voltage The parameters given in temperature and V Table 13. Embedded internal reference voltage Symbol V Internal reference voltage REFINT ADC sampling time when (1) T reading the internal reference S_vrefint voltage Internal reference voltage ...

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STM32F103xC, STM32F103xD, STM32F103xE Table 14. Maximum current consumption in Run mode, code with data processing running from Flash Symbol Parameter Supply current Run mode 1. Based on characterization, not tested in production. 2. External clock is 8 ...

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Electrical characteristics Figure 14. Typical current consumption in Run mode versus frequency (at 3 code with data processing running from RAM, peripherals enabled -45 Figure 15. Typical current consumption in ...

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STM32F103xC, STM32F103xD, STM32F103xE Table 16. Maximum current consumption in Sleep mode, code running from Flash or RAM Symbol Parameter Supply current Sleep mode 1. Based on characterization, tested in production External clock is 8 ...

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Electrical characteristics Table 17. Typical and maximum current consumptions in Stop and Standby modes Symbol Parameter Regulator in run mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) Supply current in Stop mode Regulator in ...

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STM32F103xC, STM32F103xD, STM32F103xE Figure 17. Typical current consumption in Stop mode with regulator in run mode versus temperature at different V 700 600 500 400 300 200 100 0 Figure 18. Typical current consumption in Stop mode with regulator in ...

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Electrical characteristics Figure 19. Typical current consumption in Standby mode versus temperature at different V 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -45 Typical current consumption The MCU is placed under the following conditions: ● All I/O ...

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STM32F103xC, STM32F103xD, STM32F103xE Table 18. Typical current consumption in Run mode, code with data processing running from Flash Symbol Parameter Supply I current in DD Run mode 1. Typical values are measures Add an additional power consumption ...

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Electrical characteristics Table 19. Typical current consumption in Sleep mode, coderunning from Flash or RAM Symbol Parameter Supply I current in DD Sleep mode 1. Typical values are measures Add an additional power consumption of 0.8 mA ...

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STM32F103xC, STM32F103xD, STM32F103xE On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in under the following conditions: ● all I/O pins are in input mode with a static value at V ● all peripherals are disabled ...

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Electrical characteristics Table 20. Peripheral current consumption Peripheral APB2 MHz, f HCLK 2. Specific conditions for ADC the ADC_CR2 register is set to 1. 5.3.6 External clock source characteristics High-speed external user clock generated ...

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STM32F103xC, STM32F103xD, STM32F103xE Low-speed external user clock generated from an external source The characteristics given in external clock source, and under ambient temperature and supply voltage conditions summarized in Table Table 22. Low-speed external user clock characteristics Symbol User External ...

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Electrical characteristics Figure 21. Low-speed external clock source AC timing diagram V LSEH 90% 10% V LSEL t r(LSE) EXTER NAL CLOCK SOURC E High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied ...

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STM32F103xC, STM32F103xD, STM32F103xE same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C can be used as a rough estimate of the combined pin and board capacitance) when sizing C and C . ...

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Electrical characteristics C is the pin capacitance and board or trace PCB-related capacitance. Typically stray between 2 pF and 7 pF. Caution: To avoid exceeding the maximum value use a resonator with a load capacitance ...

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STM32F103xC, STM32F103xD, STM32F103xE Low-speed internal (LSI) RC oscillator Table 26. LSI oscillator characteristics Symbol (2) f Frequency LSI (3) t LSI oscillator startup time su(LSI) (3) I LSI oscillator power consumption DD(LSI –40 ...

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Electrical characteristics 5.3.8 PLL characteristics The parameters given in temperature and V Table 28. PLL characteristics Symbol PLL input clock f PLL_IN PLL input clock duty cycle f PLL multiplier output clock PLL_OUT t PLL lock time LOCK Jitter Cycle-to-cycle ...

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STM32F103xC, STM32F103xD, STM32F103xE Table 30. Flash memory endurance and data retention Symbol Parameter N Endurance END t Data retention RET 1. Based on characterization not tested in production. 2. Cycling performed over the whole temperature range. 5.3.10 FSMC characteristics Asynchronous ...

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Electrical characteristics Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms FSMC_NE FSMC_NOE FSMC_NWE FSMC_A[25:0] FSMC_NBL[1:0] FSMC_D[15:0] FSMC_NADV 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings Symbol t FSMC_NE ...

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STM32F103xC, STM32F103xD, STM32F103xE Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms FSMC_NEx FSMC_NOE FSMC_NWE FSMC_A[25:0] FSMC_NBL[1:0] FSMC_D[15:0] FSMC_NADV 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings Symbol t ...

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Electrical characteristics Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms FSMC_NE FSMC_NOE FSMC_NWE FSMC_A[25:16] FSMC_NBL[1:0] FSMC_ AD[15:0] FSMC_NADV Table 33. Asynchronous multiplexed PSRAM/NOR read timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to FSMC_NOE low v(NOE_NE) t FSMC_NOE low ...

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STM32F103xC, STM32F103xD, STM32F103xE Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms FSMC_NEx FSMC_NOE FSMC_NWE FSMC_A[25:16] FSMC_NBL[1:0] FSMC_ AD[15:0] FSMC_NADV Table 34. Asynchronous multiplexed PSRAM/NOR write timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to FSMC_NWE low v(NWE_NE) t FSMC_NWE ...

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Electrical characteristics Synchronous waveforms and timings Figure 28 through Table 38 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: ● BurstAccessMode = FSMC_BurstAccessMode_Enable; ● MemoryType = FSMC_MemoryType_CRAM; ● WriteBurst = FSMC_WriteBurst_Enable; ...

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STM32F103xC, STM32F103xD, STM32F103xE Table 35. Synchronous multiplexed NOR/PSRAM read timings Symbol t FSMC_CLK period w(CLK) t FSMC_CLK low to FSMC_NEx low (x = 0...2) d(CLKL-NExL) t FSMC_CLK high to FSMC_NEx high (x = 0...2) d(CLKH-NExH) t FSMC_CLK low to FSMC_NADV ...

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Electrical characteristics Figure 29. Synchronous multiplexed PSRAM write timings t w(CLK) FSMC_CLK FSMC_NEx t d(CLKL-NADVL) FSMC_NADV FSMC_A[25:16] FSMC_NWE t d(CLKL-ADV) FSMC_AD[15:0] FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) FSMC_NBL 68/123 STM32F103xC, STM32F103xD, STM32F103xE t w(CLK) Data latency = 1 t ...

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STM32F103xC, STM32F103xD, STM32F103xE Table 36. Synchronous multiplexed PSRAM write timings Symbol t w(CLK) t d(CLKL-NExL) t d(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NWEL) t d(CLKH-NWEH) t d(CLKL-ADV) t d(CLKL-ADIV) t d(CLKL-Data) t su(NWAITV-CLKH) t h(CLKH-NWAITV) t ...

Page 70

Electrical characteristics Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings t w(CLK) FSMC_CLK t d(CLKL-NExL) FSMC_NEx t d(CLKL-NADVL) FSMC_NADV FSMC_A[25:0] FSMC_NOE FSMC_D[15:0] FSMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) Table 37. Synchronous non-multiplexed NOR/PSRAM ...

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STM32F103xC, STM32F103xD, STM32F103xE Figure 31. Synchronous non-multiplexed PSRAM write timings t w(CLK) FSMC_CLK t d(CLKL-NExL) FSMC_NEx t d(CLKL-NADVL) FSMC_NADV FSMC_A[25:0] FSMC_NWE FSMC_D[15:0] FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) FSMC_NBL Table 38. Synchronous non-multiplexed PSRAM write timings Symbol t w(CLK) ...

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Electrical characteristics PC Card/CompactFlash controller waveforms and timings Figure 32 through corresponding timings. The results shown in this table are obtained with the following FSMC configuration: ● COM.FSMC_SetupTime = 0x04; ● COM.FSMC_WaitSetupTime = 0x07; ● COM.FSMC_HoldSetupTime = 0x04; ● COM.FSMC_HiZSetupTime ...

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STM32F103xC, STM32F103xD, STM32F103xE Figure 33. PC Card/CompactFlash controller waveforms for common memory write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NREG FSMC_NIOWR FSMC_NIORD t d(NCE4_1-NWE) FSMC_NWE FSMC_NOE FSMC_D[15:0] High t v(NCE4_1-A) t d(NREG-NCE4_1) t d(NIORD-NCE4_1) t w(NWE) MEMxHIZ =1 t v(NWE-D) Doc ID ...

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Electrical characteristics Figure 34. PC Card/CompactFlash controller waveforms for attribute memory read access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD FSMC_NREG FSMC_NWE t d(NCE4_1-NOE) FSMC_NOE (1) FSMC_D[15:0] 1. Only data bits 0...7 are read (bits 8...15 are disregarded). 74/123 STM32F103xC, STM32F103xD, STM32F103xE ...

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STM32F103xC, STM32F103xD, STM32F103xE Figure 35. PC Card/CompactFlash controller waveforms for attribute memory write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD FSMC_NREG t d(NCE4_1-NWE) FSMC_NWE FSMC_NOE FSMC_D[7:0](1) 1. Only data bits 0...7 are driven (bits 8...15 remains HiZ). Figure 36. PC Card/CompactFlash ...

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Electrical characteristics Figure 37. PC Card/CompactFlash controller waveforms for I/O space write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NREG FSMC_NWE FSMC_NOE FSMC_NIORD t d(NCE4_1-NIOWR) FSMC_NIOWR FSMC_D[15:0] Table 39. Switching characteristics for PC Card/CF read and write cycles Symbol FSMC_NCEx low (x = ...

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STM32F103xC, STM32F103xD, STM32F103xE Table 39. Switching characteristics for PC Card/CF read and write cycles Symbol t FSMC_NIOWR low width w(NIOWR) t FSMC_NIOWR low to FSMC_D[15:0] valid v(NIOWR-D) t FSMC_NIOWR high to FSMC_D[15:0] invalid h(NIOWR-D) t FSMC_NCE4_1 low to FSMC_NIOWR valid ...

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Electrical characteristics Figure 38. NAND controller waveforms for read access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE FSMC_NOE (NRE) FSMC_D[15:0] Figure 39. NAND controller waveforms for write access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE FSMC_NOE (NRE) FSMC_D[15:0] Figure 40. NAND controller ...

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STM32F103xC, STM32F103xD, STM32F103xE Figure 41. NAND controller waveforms for common memory write access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE FSMC_NOE FSMC_D[15:0] Table 40. Switching characteristics for NAND Flash read and write cycles Symbol (2) t FSMC_D[15:0] valid before FSMC_NWE high ...

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Electrical characteristics 5.3.11 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by ...

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STM32F103xC, STM32F103xD, STM32F103xE Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ...

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Electrical characteristics Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: ● A supply overvoltage is applied to each power supply pin ● A current injection is applied to each input, output and ...

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STM32F103xC, STM32F103xD, STM32F103xE All I/Os are CMOS and TTL compliant (no software configuration required), their characteristics consider the most strict CMOS-technology or TTL parameters: ● For – the [2. 3.08 V] ...

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Electrical characteristics Table 46. Output voltage characteristics Symbol Output low level voltage for an I/O pin ( when 8 pins are sunk at same time Output high level voltage for an I/O pin ( when 8 ...

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STM32F103xC, STM32F103xD, STM32F103xE Input/output AC characteristics The definition and values of input/output AC characteristics are given in Table 47, respectively. Unless otherwise specified, the parameters given in performed under ambient temperature and V Table 10. Table 47. I/O AC characteristics ...

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Electrical characteristics Figure 42. I/O AC characteristics definition EXT ERNAL OUTPUT ON 50pF Maximum frequency is achieved 2/3)T and if the duty cycle is (45-55%) 5.3.14 NRST pin characteristics The NRST pin input ...

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STM32F103xC, STM32F103xD, STM32F103xE 5.3.15 TIM timer characteristics The parameters given in Refer to Section 5.3.13: I/O port characteristics function characteristics (output compare, input capture, external clock, PWM output). Table 49. TIMx Symbol t Timer resolution time res(TIM) Timer external clock ...

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Electrical characteristics 5.3.16 Communications interfaces interface characteristics Unless otherwise specified, the parameters given in performed under ambient temperature, f summarized in Table The STM32F103xC, STM32F103xD and STM32F103xE performance line I meets the requirements of the standard I ...

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STM32F103xC, STM32F103xD, STM32F103xE 2 Figure 44 bus AC waveforms and measurement circuit bus S TART SDA t f(SDA) t h(STA) SCL t w(SCKH) 1. Measurement points are done at CMOS levels: 0.3V Table 51. SCL ...

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Electrical characteristics SPI characteristics Unless otherwise specified, the parameters given in are derived from tests performed under ambient temperature, f supply voltage conditions summarized in Refer to Section 5.3.13: I/O port characteristics function characteristics (NSS, SCK, ...

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STM32F103xC, STM32F103xD, STM32F103xE Figure 45. SPI timing diagram - slave mode and CPHA = 0 NSS input t SU(NSS) CPHA= 0 CPOL=0 t w(SCKH) CPHA w(SCKL) CPOL=1 t a(SO) MISO OUT su(SI) MOSI I NPUT ...

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Electrical characteristics Figure 47. SPI timing diagram - master mode High NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 t su(MI) MISO INP UT MOSI OUTPUT 1. Measurement points are done at CMOS levels: 0.3V 92/123 ...

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STM32F103xC, STM32F103xD, STM32F103xE 2 Table 53 characteristics Symbol Parameter I2S slave input clock duty DuCy(SCK) cycle clock frequency 1/t c(CK r(CK clock rise and fall time t f(CK) (1) ...

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Electrical characteristics 2 Figure 48 slave timing diagram (Philips protocol) CPOL = 0 CPOL = 1 WS input SD transmit SD receive 1. Measurement points are done at CMOS levels: 0.3 × LSB transmit/receive of the ...

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STM32F103xC, STM32F103xD, STM32F103xE SD/SDIO MMC card host interface (SDIO) characteristics Unless otherwise specified, the parameters given in performed under ambient temperature, f summarized in Table Refer to Section 5.3.13: I/O port characteristics function characteristics (D[7:0], CMD, CK). Figure 50. SDIO ...

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Electrical characteristics Table 54 MMC characteristics Symbol Clock frequency in data transfer f PP mode t Clock low time, f W(CKL) t Clock high time, f W(CKH) t Clock rise time r t Clock fall time f CMD, ...

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STM32F103xC, STM32F103xD, STM32F103xE Table 56. USB DC electrical characteristics Symbol Input levels V USB operating voltage DD (4) V Differential input sensitivity DI (4) V Differential common mode range Includes V CM (4) V Single ended receiver threshold SE Output ...

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Electrical characteristics 5.3.18 12-bit ADC characteristics Unless otherwise specified, the parameters given in performed under ambient temperature, f conditions summarized in Note recommended to perform a calibration after each power-up. Table 58. ADC characteristics Symbol Parameter V Power ...

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STM32F103xC, STM32F103xD, STM32F103xE Equation 1: R AIN  R ------------------------------------------------------------- - R AIN  ADC The formula above error below 1/4 of LSB. Here (from 12-bit resolution). Table 59. R AIN T (cycles) s 1.5 ...

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Electrical characteristics Table 61. ADC accuracy Symbol ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error 1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could be ...

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STM32F103xC, STM32F103xD, STM32F103xE Figure 54. Typical connection diagram using the ADC R AIN (1) V AIN 1. Refer to Table represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the parasitic pad ...

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Electrical characteristics Figure 56. Power supply and reference decoupling ( and V REF+ REF– 102/123 STM32F103xC, STM32F103xD, STM32F103xE 1 µ inputs are available only on 100-pin packages. Doc ID 14611 Rev connected ...

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STM32F103xC, STM32F103xD, STM32F103xE 5.3.19 DAC electrical specifications Table 62. DAC characteristics Symbol Parameter V Analog supply voltage DDA V Reference supply voltage REF+ V Ground SSA (1) R Resistive load with buffer ON 5 LOAD Impedance output with buffer (1) ...

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Electrical characteristics Table 62. DAC characteristics (continued) Symbol Parameter Offset error (difference between (2) Offset measured value at Code (0x800) and the ideal value = V /2) REF+ Gain Gain error (2) error Settling time (full scale: for a 10-bit ...

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STM32F103xC, STM32F103xD, STM32F103xE 5.3.20 Temperature sensor characteristics Table 63. TS characteristics Symbol ( SENSE (1) Avg_Slope Average slope (1) V Voltage at 25 °C 25 (2) t Startup time START ADC sampling time when reading the (3)(2) ...

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Package characteristics 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status ...

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STM32F103xC, STM32F103xD, STM32F103xE Figure 59. LFBGA144 – 144-ball low profile fine pitch ball grid array mm, 0.8 mm pitch, package outline 1. Drawing is not to scale. Table 64. LFBGA144 – 144-ball low profile fine pitch ball ...

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Package characteristics Figure 60. LFBGA100 - low profile fine pitch ball grid array package outline 1. Drawing is not to scale. Table 65. LFBGA100 - low profile fine pitch ball grid array ...

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STM32F103xC, STM32F103xD, STM32F103xE Figure 61. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline A1 ball corner H Marking area Wafer back side Ball eee 1. Drawing is not to scale. 2. Primary datum Z and ...

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Package characteristics Figure 62. Recommended PCB design rules (0.5 mm pitch BGA) Dpad 110/123 STM32F103xC, STM32F103xD, STM32F103xE Dpad Dsm Solder paste – Non solder mask defined pads are recommended – mils screen print Dsm Doc ID 14611 ...

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STM32F103xC, STM32F103xD, STM32F103xE Figure 63. LQFP144 mm, 144-pin low-profile quad flat package outline Seating plane ccc 108 109 144 Pin 1 1 identification 1. Drawing is not to ...

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Package characteristics Figure 65. LQFP100 100-pin low-profile quad flat package outline 100 26 Pin identification e 1. Drawing is not to scale. 2. Dimensions are in ...

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STM32F103xC, STM32F103xD, STM32F103xE Figure 67. LQFP64 – pin low-profile quad flat package outline Drawing is not to scale. 2. Dimensions are in millimeters. Table 69. LQFP64 – ...

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Package characteristics 6.2 Thermal characteristics The maximum chip junction temperature (T Table 10: General operating conditions on page The maximum chip-junction temperature, T using the following equation: Where: ● T max is the maximum ambient temperature in °C, A  ...

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STM32F103xC, STM32F103xD, STM32F103xE 6.2.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, ...

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Package characteristics Using the values obtained in – For LQFP100, 46 °C 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C Jmax This is within the range of the suffix ...

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STM32F103xC, STM32F103xD, STM32F103xE 7 Part numbering Table 71. Ordering information scheme Example: Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 103 = performance line Pin count pins V = 100 pins ...

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Revision history 8 Revision history Table 72. Document revision history Date Revision 07-Apr-2008 22-May-2008 118/123 STM32F103xC, STM32F103xD, STM32F103xE 1 Initial release. Document status promoted from Target Specification to Preliminary Data. Section 1: Introduction and the family modified. Small text changes. ...

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STM32F103xC, STM32F103xD, STM32F103xE Table 72. Document revision history Date Revision 21-Jul-2008 Document status promoted from Preliminary Data to full datasheet. FSMC (flexible static memory controller) on page 15 Number of complementary channels corrected in STM32F103xC, STM32F103xD and STM32F103xE performance line ...

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Revision history Table 72. Document revision history Date Revision 12-Dec-2008 120/123 STM32F103xC, STM32F103xD, STM32F103xE Timers specified on page 1 Section 2.2: Full compatibility throughout the family Table 4: High-density timer feature comparison General-purpose timers (TIMx) TIM8) on page 19 updated. ...

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STM32F103xC, STM32F103xD, STM32F103xE Table 72. Document revision history Date Revision 30-Mar-2009 I/O information clarified on page STM32F103xE performance line BGA100 ballout I/O information clarified on page In Table 5: High-density STM32F103xx pin – I/O level of pins PF11, PF12, PF13, ...

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Revision history Table 72. Document revision history Date Revision 21-Jul-2009 24-Sep-2009 122/123 STM32F103xC, STM32F103xD, STM32F103xE Figure 1: STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram Note 5 updated and Note 4 STM32F103xx pin definitions. V and T added to RERINT ...

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... STM32F103xC, STM32F103xD, STM32F103xE Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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