C8051F220-GQ Silicon Laboratories Inc, C8051F220-GQ Datasheet - Page 71

• Manufacturer Part Number: C8051F220-GQ
• Description: IC 8051 MCU 8K FLASH 48TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F2xxr

Specifications of C8051F220-GQ

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 48-TQFP, 48-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 32
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 32x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F2x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F206DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 32-ch x 8-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1241 - DEV KIT F220/221/226/230/231/236
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1238

9.3.1. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved
bits should be set to logic 0. Future product versions may use these bits to implement new features in
which case the reset value of the bit will be logic 0, selecting the feature’s default state. Detailed descrip-
tions of the remaining SFRs are included in the sections of the datasheet associated with their correspond-
ing system function.
Bits 7–0: SP: Stack Pointer. 
Bits 7–0: DPL: Data Pointer Low. 
Bits 7–0: DPH: Data Pointer High. 
R/W
R/W
R/W
Bit7
Bit7
Bit7
The stack pointer holds the location of the top of the stack. The stack pointer is incremented
before every PUSH operation. The SP register defaults to 0x07 after reset.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed RAM.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed RAM.
R/W
R/W
R/W
Bit6
Bit6
Bit6
SFR Definition 9.3. DPH: Data Pointer High Byte
SFR Definition 9.2. DPL: Data Pointer Low Byte
R/W
R/W
R/W
Bit5
Bit5
Bit5
SFR Definition 9.1. SP: Stack Pointer
R/W
R/W
R/W
Bit4
Bit4
Bit4
Rev. 1.6
R/W
R/W
R/W
Bit3
Bit3
Bit3
R/W
R/W
R/W
Bit2
Bit2
Bit2
R/W
R/W
R/W
Bit1
Bit1
Bit1
C8051F2xx
R/W
R/W
R/W
Bit0
Bit0
Bit0
SFR Address:
SFR Address:
SFR Address:
Reset Value
Reset Value
Reset Value
00000111
00000111
00000111
0x81
0x81
0x81
71