C8051F34C-GQ Silicon Laboratories Inc, C8051F34C-GQ Datasheet - Page 105

• Manufacturer Part Number: C8051F34C-GQ
• Description: IC 8051 MCU 64K FLASH 48TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F34xr

Specifications of C8051F34C-GQ

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 48-TQFP, 48-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 40
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Ram Size: 256 KB
• Interface Type: UART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F340DK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
Note: For bits that act as both reset source enables (on a write) and reset indicator flags (on a
read), read-modify-write instructions read and modify the source enable only. This applies to
bits: USBRSF, C0RSEF, SWRSF, MCDRSF, PORSF.
USBRSF FERROR C0RSEF
R/W
Bit7
USBRSF: USB Reset Flag
0: Read: Last reset was not a USB reset; Write: USB resets disabled.
1: Read: Last reset was a USB reset; Write: USB resets enabled.
FERROR: Flash Error Indicator.
0: Source of last reset was not a Flash read/write/erase error.
1: Source of last reset was a Flash read/write/erase error.
C0RSEF: Comparator0 Reset Enable and Flag.
0: Read: Source of last reset was not Comparator0; Write: Comparator0 is not a reset
source.
1: Read: Source of last reset was Comparator0; Write: Comparator0 is a reset source
(active-low).
SWRSF: Software Reset Force and Flag.
0: Read: Source of last reset was not a write to the SWRSF bit; Write: No Effect.
1: Read: Source of last was a write to the SWRSF bit; Write: Forces a system reset.
WDTRSF: Watchdog Timer Reset Flag.
0: Source of last reset was not a WDT timeout.
1: Source of last reset was a WDT timeout.
MCDRSF: Missing Clock Detector Flag.
0: Read: Source of last reset was not a Missing Clock Detector timeout; Write: Missing
Clock Detector disabled.
1: Read: Source of last reset was a Missing Clock Detector timeout; Write: Missing Clock
Detector enabled; triggers a reset if a missing clock condition is detected.
PORSF: Power-On / V
This bit is set anytime a power-on reset occurs. Writing this bit selects/deselects the V
monitor as a reset source. Note: writing ‘1’ to this bit before the V
and stabilized can cause a system reset. See register VDM0CN (SFR Definition 11.1).
0: Read: Last reset was not a power-on or V
reset source.
1: Read: Last reset was a power-on or V
Write: V
PINRSF: HW Pin Reset Flag.
0: Source of last reset was not RST pin.
1: Source of last reset was RST pin.
Bit6
R
DD
monitor is a reset source.
SFR Definition 11.2. RSTSRC: Reset Source
R/W
Bit5
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
DD
SWRSF
Monitor Reset Flag.
R/W
Bit4
WDTRSF MCDRSF
Rev. 1.3
Bit3
DD
R
monitor reset; all other reset flags indeterminate;
DD
monitor reset; Write: V
R/W
Bit2
PORSF
R/W
Bit1
DD
PINRSF
DD
monitor is enabled
Bit0
R
monitor is not a
SFR Address:
Reset Value
Variable
0xEF
DD
105