C8051F044-GQR Silicon Laboratories Inc, C8051F044-GQR Datasheet - Page 236

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C8051F044-GQR

Manufacturer Part Number
C8051F044-GQR
Description
IC 8051 MCU 64K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Datasheets

Specifications of C8051F044-GQR

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F044-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
C8051F040/1/2/3/4/5/6/7
236
Bit 4:
R/W
R/W
Bit7
Bit7
*
Please see the Bosch CAN User’s Guide for a complete definition of this register
CANIF: CAN Interrupt Flag. Write = don’t care.
0: CAN interrupt has not occurred.
1: CAN interrupt has occurred and is active.
CANIF is controlled by the CAN controller and is cleared by hardware once all interrupt con-
ditions have been cleared in the CAN controller. See Section 3.4.1 in the Bosch CAN User’s
Guide (page 24) for more information concerning CAN controller interrupts.
*All CAN registers’ functions/definitions are listed and described in the Bosch CAN
User’s Guide with the exception of the CANIF bit.
This register may be accessed directly in the CIP-51 SFR register space, or through the indi-
rect, index method (See Section
Access CAN
All CAN registers’ functions/definitions are listed and described in the Bosch CAN
User’s Guide.
This register may be accessed directly in the CIP-51 SFR register space, or through the indi-
rect, index method (See Section
Access CAN
R/W
R/W
Bit6
Bit6
*
SFR Definition 18.3. CAN0CN: CAN Control
Registers” on page 232).
Registers” on page 232).
SFR Definition 18.4. CAN0TST: CAN Test
R/W
R/W
Bit5
Bit5
*
CANIF
R/W
Bit4
Bit4
R
“18.2.5. Using CAN0ADR, CAN0DATH, and CANDATL to
“18.2.5. Using CAN0ADR, CAN0DATH, and CANDATL to
Rev. 1.5
R/W
R/W
Bit3
Bit3
*
R/W
R/W
Bit2
Bit2
*
R/W
R/W
Bit1
Bit1
*
SFR Address:
SFR Address:
SFR Page:
SFR Page:
R/W
R/W
Bit0
Bit0
*
0xF8
1
0xDB
1
Reset Value
Reset Value

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