C8051F041-GQR Silicon Laboratories Inc, C8051F041-GQR Datasheet
C8051F041-GQR
Manufacturer Part Number
C8051F041-GQR
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Specifications of C8051F041-GQR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 13x12b; D/A 2x10b, 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
336-1205 - DEV KIT FOR F040/F041/F042/F043
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F041-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Analog Peripherals
12-Bit ADC
-
-
-
-
-
-
High-Voltage Differential Amplifier
-
-
-
8-Bit ADC
-
-
-
Two 12-Bit DACs
Three Comparators
Internal Voltage Reference
Precision V
On-Chip JTAG Debug & Boundary Scan
-
-
-
-
-
CAN 2.0B
±1 LSB INL; guaranteed monotonic
Programmable throughput up to 100 ksps
13 external inputs; programmable as single-ended or differential
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
Data-dependent windowed interrupt generator
Built-in temperature sensor (±3 °C)
60 V common mode input range
Offset adjust from –60 to +60 V
16 gain settings from 0.05 to 16
Programmable throughput up to 500 ksps
8 external inputs; programmable as single-ended or differential
Programmable amplifier gain: 4, 2, 1, 0.5
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping, watchpoints, stack monitor, pro-
gram trace memory
Inspect/modify memory and registers
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
IEEE1149.1 compliant boundary scan
MONEN
HVAIN+
VREFA
HVREF
HVCAP
HVAIN-
XTAL1
XTAL2
AIN0.0
AIN0.1
AIN0.2
AIN0.3
DGND
DGND
DGND
AGND
AGND
VREF
DAC1
DAC0
VDD
VDD
VDD
TCK
TMS
TDO
AV+
AV+
RST
TDI
DD
Monitor/Brown-out Detector
Oscillator
External
Monitor
Circuit
VDD
HVAMP
Analog Power
Digital Power
M
A
U
X
JTAG
Logic
(12-Bit)
(12-Bit)
VREF
DAC0
DAC1
SENSOR
TEMP
Prog
Gain
Boundary Scan
WDT
Debug HW
Oscillator
Internal
2%
25 MIPS, 64 kB Flash, 12-Bit ADC, 64-Pin Mixed-Signal MCU
100 ksps
(12-Bit)
A
M
U
X
ADC
System
Clock
Reset
Copyright © 2004 by Silicon Laboratories
8:2
C
8
0
5
1
o
e
r
External Data Memory Bus
SFR Bus
CANRAM
256 byte
FLASH
32x136
64 kB
XRAM
RAM
4 kB
High-Speed 8051 µC Core
-
-
-
Memory
-
-
-
CAN Bus 2.0B
-
-
Digital Peripherals
-
-
-
-
-
-
Clock Sources
-
-
Supply Voltage: 2.7 to 3.6 V
-
-
64-Pin TQFP
-
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
Up to 25 MIPS throughput with 25 MHz system clock
Expanded interrupt handler
4352 bytes data RAM
64 kB Flash; in-system programmable in 512-byte sectors (512 bytes
are reserved)
External parallel data memory interface
32 message objects
”Mailbox" implementation only interrupts CPU when needed
32 port I/O; all are 5 V tolerant
Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial
ports available concurrently
Programmable 16-bit counter array with 6 capture/compare modules
5 general-purpose 16-bit counter/timers
Dedicated watchdog timer; bidirectional reset
Real-time clock mode using timer 3 or PCA
Internal programmable 2% oscillator: up to 25 MHz
External oscillator: Crystal, RC, C, or Clock
Typical operating current: 10 mA at 25 MHz
Multiple power saving sleep and shutdown mode
Temperature Range: –40 to +85 °C
0,1,2,3,4
SPI Bus
Latches
UART0
UART1
SMBus
Timers
0,1,2,3
CAN
2.0B
PCA
Port
&4
Address [15:0]
Port 4 <from crossbar>
Bus Control
Data [7:0]
VREFA
CP2
500 ksps
(8-Bit)
ADC
CP1
CP0
O
C
R
S
S
B
A
R
P5 Latch
P6 Latch
Addr [15:8]
P7 Latch
Data Latch
Addr [7:0]
Ctrl Latch
+
-
+
-
Prog
Gain
C8051F041
+
-
Drv
Drv
Drv
Drv
P0
P1
P2
P3
A
M
U
X
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
8:1
DRV
DRV
DRV
DRV
P4
P5
P6
P7
P0.0
P0.7
P1.0/AIN1.0
P1.7/AIN1.7
P2.0/CPx
P2.7/CPx
P3.0/AIN0.6
P3.7/AIN0.7
CTX0
CRX0
6.15.2004
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C8051F041-GQR Summary of contents
Page 1
... FLASH Latches C 32x136 CAN o CANRAM 2.0B 256 byte r RAM XRAM Port 4 <from crossbar> External Data Memory Bus Bus Control Address [15:0] 8:2 Data [7:0] Copyright © 2004 by Silicon Laboratories C8051F041 P0.0 P0 Drv P0 P1.0/AIN1 Drv P1.7/AIN1 P2.0/CPx P2 B Drv P2.7/CPx A R P3.0/AIN0.6 ...
Page 2
... A1 0.05 - 0.15 A2 0.95 - 1.05 b 0.17 0.22 0. 12. 10. 0. 12. 10.00 - Copyright © 2004 by Silicon Laboratories C8051F041 TYP MAX UNITS 3 0 µA 0.1 µA 25 MHz 12 bits ±1 LSB ±1 LSB 69 dB 100 ksps VREF V 12 LSB ±1 LSB 10 µs 1.5 µA 4 µ ...