C8051F040-GQR Silicon Laboratories Inc, C8051F040-GQR Datasheet - Page 301

• Manufacturer Part Number: C8051F040-GQR
• Description: IC 8051 MCU 64K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F04xr

Specifications of C8051F040-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b, 13x12b; D/A 2x10b, 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: 336-1205 - DEV KIT FOR F040/F041/F042/F043
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit7:
Bit6:
Bit5-4:
Bit3:
Bit2:
Bit1:
Bit0:
SFR Address: TMR2CN:0xC8;TMR3CN:0xC8;TMR4CN:0xC8
SFR Page: TMR2CN: page 0;TMR3CN: page 1;TMR4CN: page 2
TFn
R/W
Bit7
TFn: Timer n Overflow/Underflow Flag.
Set by hardware when either the Timer overflows from 0xFFFF to 0x0000, underflows from
the value placed in RCAPnH:RCAPnL to 0xFFFF (in Auto-reload Mode), or underflows from
0x0000 to 0xFFFF (in Capture Mode). When the Timer interrupt is enabled, setting this bit
causes the CPU to vector to the Timer interrupt service routine. This bit is not automatically
cleared by hardware and must be cleared by software.
EXFn: Timer 2, 3, or 4 External Flag.
Set by hardware when either a capture or reload is caused by a high-to-low transition on the
TnEX input pin and EXENn is logic 1. When the Timer interrupt is enabled, setting this bit
causes the CPU to vector to the Timer Interrupt service routine. This bit is not automatically
cleared by hardware and must be cleared by software.
Reserved.
EXENn: Timer n External Enable.
Enables high-to-low transitions on TnEX to trigger captures, reloads, and control the direc-
tion of the timer/counter (up or down count). If DECEN = 1, TnEX will determine if the timer
counts up or down when in Auto-reload Mode. If EXENn = 1, TnEX should be configured as
a digital input.
0: Transitions on the TnEX pin are ignored.
1: Transitions on the TnEX pin cause capture, reload, or control the direction of timer count
(up or down) as follows:
Capture Mode: ‘1’-to-’0’ Transition on TnEX pin causes RCAPnH:RCAPnL to capture timer
value.
Auto-Reload Mode:
TRn: Timer n Run Control.
This bit enables/disables the respective Timer.
0: Timer disabled.
1: Timer enabled and running/counting.
C/Tn: Counter/Timer Select.
0: Timer Function: Timer incremented by clock defined by TnM1:TnM0
(TMRnCF.4:TMRnCF.3).
1: Counter Function: Timer incremented by high-to-low transitions on external input pin.
CP/RLn: Capture/Reload Select.
This bit selects whether the Timer functions in capture or auto-reload mode.
0: Timer is in Auto-Reload Mode.
1: Timer is in Capture Mode.
EXFn
R/W
Bit6
DCEN = 0: ‘1’-to-’0’ transition causes reload of timer and sets the EXFn Flag.
DCEN = 1: TnEX logic level controls direction of timer (up or down).
SFR Definition 23.8. TMRnCN: Timer n Control
R/W
Bit5
-
R/W
Bit4
-
Rev. 1.5
EXENn
R/W
Bit3
C8051F040/1/2/3/4/5/6/7
TRn
R/W
Bit2
C/Tn
R/W
Bit1
CP/RLn 00000000
R/W
Bit0
Addressable
Reset Value
Bit
299