C8051F063-GQR Silicon Laboratories Inc, C8051F063-GQR Datasheet - Page 149

• Manufacturer Part Number: C8051F063-GQR
• Description: IC 8051 MCU 64K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F063-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b, 8x10b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: CAN, I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F060DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit, 1 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: 336-1214 - DEV KIT FOR F060/F062/F063
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Bit7:
Bit6:
Bit5:
Bits4-3:
Bit2:
Bit1:
Bit0:
R/W
Bit7
CY
CY: Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow
(subtraction). It is cleared to 0 by all other arithmetic operations.
AC: Auxiliary Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a bor-
row from (subtraction) the high order nibble. It is cleared to 0 by all other arithmetic opera-
tions.
F0: User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
RS1-RS0: Register Bank Select.
These bits select which register bank is used during register accesses.
OV: Overflow Flag.
This bit is set to 1 under the following circumstances:
• An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
• A MUL instruction results in an overflow (result is greater than 255).
• A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other
cases.
F1: User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
PARITY: Parity Flag.
This bit is set to 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum
is even.
RS1
0
0
1
1
R/W
Bit6
AC
RS0
0
1
0
1
R/W
Bit5
F0
Figure 13.16. PSW: Program Status Word
Register Bank
RS1
R/W
Bit4
0
1
2
3
Rev. 1.2
RS0
R/W
Bit3
0x00 - 0x07
0x08 - 0x0F
0x10 - 0x17
0x18 - 0x1F
Address
C8051F060/1/2/3/4/5/6/7
R/W
Bit2
OV
R/W
Bit1
F1
SFR Address:
PARITY
SFR Page:
R/W
Bit0
0xD0
All Pages
Addressable
Reset Value
00000000
Bit
149