C8051F062-GQR Silicon Laboratories Inc, C8051F062-GQR Datasheet - Page 317

• Manufacturer Part Number: C8051F062-GQR
• Description: IC 8051 MCU 64K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F062-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 59
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b, 8x10b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: 336-1214 - DEV KIT FOR F060/F062/F063
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

26.
Each MCU has an on-chip JTAG interface and logic to support boundary scan for production and in-sys-
tem testing, Flash read/write operations, and non-intrusive in-circuit debug. The JTAG interface is fully
compliant with the IEEE 1149.1 specification. Refer to this specification for detailed descriptions of the Test
Interface and Boundary-Scan Architecture. Access of the JTAG Instruction Register (IR) and Data Regis-
ters (DR) are as described in the Test Access Port and Operation of the IEEE 1149.1 specification.
The JTAG interface is accessed via four dedicated pins on the MCU: TCK, TMS, TDI, and TDO.
Through the 16-bit JTAG Instruction Register (IR), any of the eight instructions shown in Figure 26.1 can
be commanded. There are three DR’s associated with JTAG Boundary-Scan, and four associated with
Flash read/write operations on the MCU.
IR Value
0xFFFF
0x0000
0x0002
0x0004
0x0082
0x0083
0x0084 Flash Address
0x0085
Bit15
JTAG (IEEE 1149.1)
Flash Control
Flash Scale
Instruction
Flash Data
PRELOAD
SAMPLE/
EXTEST
IDCODE
BYPASS
Selects FLASHSCL Register which controls the Flash one-shot timer and
Selects FLASHCON Register to control how the interface logic responds
Selects FLASHADR Register which holds the address of all Flash read,
Figure 26.1. IR: JTAG Instruction Register
Selects the Boundary Data Register for observability and presetting the
Selects FLASHDAT Register for reads and writes to the Flash memory
Selects the Boundary Data Register for control and observability of all
to reads and writes to the FLASHDAT Register
Rev. 1.2
Selects Bypass Data Register
write, and erase operations
Selects device ID Register
C8051F060/1/2/3/4/5/6/7
read-always enable
scan-path latches
Description
device pins
Bit0
Reset Value
0x0000
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