C8051F061-GQR Silicon Laboratories Inc, C8051F061-GQR Datasheet - Page 276

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C8051F061-GQR

Manufacturer Part Number
C8051F061-GQR
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F06xr
Datasheets

Specifications of C8051F061-GQR

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 2x16b, 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F061-GQR
Manufacturer:
SILICON
Quantity:
2 100
Part Number:
C8051F061-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
C8051F060/1/2/3/4/5/6/7
276
Bits7-0:
Bits7-0:
Bits7-0:
R/W
R/W
R/W
Bit7
Bit7
Bit7
SBUF0.[7:0]: UART0 Buffer Bits 7-0 (MSB-LSB).
This is actually two registers; a transmit and a receive buffer register. When data is moved to
SBUF0, it goes to the transmit buffer and is held for serial transmission. Moving a byte to
SBUF0 is what initiates the transmission. When data is moved from SBUF0, it comes from
the receive buffer.
SADDR0.[7:0]: UART0 Slave Address.
The contents of this register are used to define the UART0 slave address. Register SADEN0
is a bit mask to determine which bits of SADDR0 are checked against a received address:
corresponding bits set to logic 1 in SADEN0 are checked; corresponding bits set to logic 0
are “don’t cares”.
SADEN0.[7:0]: UART0 Slave Address Enable.
Bits in this register enable corresponding bits in register SADDR0 to determine the UART0
slave address.
0: Corresponding bit in SADDR0 is a “don’t care”.
1: Corresponding bit in SADDR0 is checked against a received address.
R/W
R/W
R/W
Bit6
Bit6
Bit6
Figure 22.12. SADEN0: UART0 Slave Address Enable Register
Figure 22.11. SADDR0: UART0 Slave Address Register
Figure 22.10. SBUF0: UART0 Data Buffer Register
R/W
R/W
R/W
Bit5
Bit5
Bit5
R/W
R/W
R/W
Bit4
Bit4
Bit4
Rev. 1.2
R/W
R/W
R/W
Bit3
Bit3
Bit3
R/W
R/W
R/W
Bit2
Bit2
Bit2
R/W
R/W
R/W
Bit1
Bit1
Bit1
SFR Address:
SFR Address:
SFR Address:
SFR Page:
SFR Page:
SFR Page:
R/W
R/W
Bit0
R/W
Bit0
Bit0
0x99
0
0xB9
0
0xA9
0
Reset Value
Reset Value
00000000
Reset Value
00000000
00000000

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