AT90S2313-10SC Atmel, AT90S2313-10SC Datasheet - Page 16

• Manufacturer Part Number: AT90S2313-10SC
• Description: MCU 2K FLASH 10MHZ 20-SOIC
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S2313-10SC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Status Register – SREG
16
AT90S2313
Table 1. AT90S2313 I/O Space
Note:
All AT90S2313 I/O and peripherals are placed in the I/O space. The I/O locations are
accessed by the IN and OUT instructions transferring data between the 32 general pur-
pose working registers and the I/O space. I/O Registers within the address range $00 -
$1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the
value of single bits can be checked by using the SBIS and SBIC instructions. Refer to
the instruction set section for more details. When using the I/O specific commands IN
and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O Registers as
SRAM, $20 must be added to this address. All I/O Register addresses throughout this
document are shown with the SRAM address in parentheses.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical “1” to them. Note that the CBI
and SBI instructions will operate on all bits in the I/O Register, writing a “1” back into any
flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers
$00 to $1F only.
The I/O and peripherals control registers are explained in the following sections.
The AVR Status Register (SREG) at I/O space location $3F ($5F) is defined as:
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set (one) for the interrupts to be enabled. The
individual interrupt enable control is then performed in separate control registers. If the
Global Interrupt Enable bit is cleared (zero), none of the interrupts are enabled indepen-
dent of the individual interrupt enable settings. The I-bit is cleared by hardware after an
interrupt has occurred, and is set by the RETI instruction to enable subsequent
interrupts.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source
and destination for the operated bit. A bit from a register in the Register File can be cop-
ied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the
Register File by the BLD instruction.
Bit
$3F ($5F)
Read/Write
Initial value
Address Hex
$0C ($2C)
$0B ($2B)
$0A ($2A)
$12 ($32)
$11 ($31)
$10 ($30)
$09 ($29)
$08 ($28)
1. Reserved and unused locations are not shown in the table.
R/W
7
0
I
PORTD
DDRD
UBRR
Name
ACSR
PIND
UDR
UCR
USR
R/W
6
T
0
(1)
R/W
H
5
0
Function
Data Direction Register, Port D
Input Pins, Port D
UART I/O Data Register
UART Control Register
Analog Comparator Control and Status Register
Data Register, Port D
UART Status Register
UART Baud Rate Register
(Continued)
R/W
S
4
0
R/W
V
3
0
R/W
N
2
0
R/W
1
Z
0
R/W
C
0
0
0839I–AVR–06/02
SREG