AT90S8515-4PC Atmel, AT90S8515-4PC Datasheet - Page 37

• Manufacturer Part Number: AT90S8515-4PC
• Description: IC MCU 8K FLSH 4MHZ LV 40DIP
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S8515-4PC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Timer/Counter1 Control
Register B – TCCR1B
0841G–09/01
• Bit 7 – ICNC1: Input Capture1 Noise Canceler (4 CKs)
When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is
disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP
(input capture pin) as specified. When the ICNC1 bit is set (one), four successive sam-
ples are measured on the ICP, and all samples must be high/low according to the input
capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL
clock frequency.
• Bit 6 – ICES1: Input Capture1 Edge Select
While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the
Input Capture Register (ICR1) on the falling edge of the input capture pin (ICP). While
the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the ICR1 on
the rising edge of the ICP.
• Bits 5, 4 – Res: Reserved Bits
These bits are reserved bits in the AT90S8515 and always read zero.
• Bit 3 – CTC1: Clear Timer/Counter1 on Compare Match
When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock
cycle after a compareA match. If the CTC1 control bit is cleared, Timer/Counter1 contin-
ues counting and is unaffected by a compare match. Since the compare match is
detected in the CPU clock cycle following the match, this function will behave differently
when a prescaling higher than 1 is used for the timer. When a prescaling of 1 is used,
and the compareA register is set to C, the timer will count as follows if CTC1 is set:
... | C-2 | C-1 | C | 0 | 1 | ...
When the prescaler is set to divide by 8, the timer will count like this:
... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0,
0, 0, 0, 0, 0, 0 | ...
In PWM mode, this bit has no effect.
• Bits 2, 1, 0 – CS12, CS11, CS10: Clock Select1, Bits 2, 1 and 0
The Clock Select1 bits 2, 1 and 0 define the prescaling source of Timer/Counter1.
Table 10. Clock 1 Prescale Select
Bit
$2E ($4E)
Read/Write
Initial Value
CS12
0
0
0
0
1
1
1
1
ICNC1
R/W
CS11
7
0
0
0
1
1
0
0
1
1
ICES1
R/W
6
0
CS10
0
1
0
1
0
1
0
1
R
5
–
0
Description
Stop, the Timer/Counter1 is stopped.
CK
CK/8
CK/64
CK/256
CK/1024
External Pin T1, falling edge
External Pin T1, rising edge
R
4
–
0
CTC1
R/W
3
0
CS12
R/W
2
0
CS11
R/W
1
0
AT90S8515
CS10
R/W
0
0
TCCR1B
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