AT90S8515-8PC Atmel, AT90S8515-8PC Datasheet - Page 66

• Manufacturer Part Number: AT90S8515-8PC
• Description: IC MCU 8K FLSH 8MHZ 40DIP
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S8515-8PC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Port B as General Digital I/O
Alternate Functions of Port B
66
AT90S8515
All eight pins in Port B have equal functionality when used as digital I/O pins.
PBn, general I/O pin: The DDBn bit in the DDRB register selects the direction of this pin.
If DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero), PBn
is configured as an input pin. If PORTBn is set (one) when the pin is configured as an
input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the
PORTBn has to be cleared (zero) or the pin has to be configured as an output pin. The
Port B pins are tri-stated when a reset condition becomes active, even if the clock is not
active.
Table 21. DDBn Effects on Port B Pins
Note:
The alternate pin configuration is as follows:
• SCK – Port B, Bit 7
SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is
enabled as a slave, this pin is configured as an input regardless of the setting of DDB7.
When the SPI is enabled as a master, the data direction of this pin is controlled by
DDB7. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB7 bit. See the description of the SPI port for further details.
• MISO – Port B, Bit 6
MISO: Master data input, slave data output pin for SPI channel. When the SPI is
enabled as a master, this pin is configured as an input regardless of the setting of
DDB6. When the SPI is enabled as a slave, the data direction of this pin is controlled by
DDB6. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB6 bit. See the description of the SPI port for further details.
• MOSI – Port B, Bit 5
MOSI: SPI Master data output, slave data input for SPI channel. When the SPI is
enabled as a slave, this pin is configured as an input regardless of the setting of DDB5.
When the SPI is enabled as a master, the data direction of this pin is controlled by
DDB5. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB5 bit. See the description of the SPI port for further details.
• SS – Port B, Bit 4
SS: Slave port select input. When the SPI is enabled as a slave, this pin is configured as
an input regardless of the setting of DDB4. As a slave, the SPI is activated when this pin
is driven low. When the SPI is enabled as a master, the data direction of this pin is con-
trolled by DDB4. When the pin is forced to be an input, the pull-up can still be controlled
by the PORTB4 bit. See the description of the SPI port for further details.
• AIN1 – Port B, Bit 3
AIN1: Analog Comparator Negative Input. When configured as an input (DDB3 is
cleared [zero]) and with the internal MOS pull-up resistor switched off (PB3 is cleared
[zero]), this pin also serves as the negative input of the On-chip Analog Comparator.
DDBn
0
0
1
1
n: 7,6…0, pin number.
PORTBn
0
1
0
1
Output
Output
Input
Input
I/O
Pull up
Yes
No
No
No
Tri-state (high-Z)
PBn will source current if ext. pulled low.
Push-pull One Output
Comment
Push-pull Zero Output
0841G–09/01