AT90S8515A-8PC Atmel, AT90S8515A-8PC Datasheet

AT90S8515A-8PC

Manufacturer Part Number

AT90S8515A-8PC

Description

IC MCU 8K FLSH 8MHZ 40DIP

Manufacturer

Atmel

Series

AVR® 90Sr

Datasheets

1.AT90S8515-4AC.pdf (112 pages)

2.AT90S8515-4AC.pdf (4 pages)

3.AT90S8515-4AC.pdf (4 pages)

Specifications of AT90S8515A-8PC

Core Processor

AVR

Core Size

8-Bit

Speed

8MHz

Connectivity

SPI, UART/USART

Peripherals

Brown-out Detect/Reset, POR, PWM, WDT

Number Of I /o

Program Memory Size

8KB (4K x 16)

Program Memory Type

FLASH

Eeprom Size

512 x 8

Ram Size

512 x 8

Voltage - Supply (vcc/vdd)

4 V ~ 6 V

Oscillator Type

Internal

Operating Temperature

0°C ~ 70°C

Package / Case

40-DIP (0.600", 15.24mm)

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Data Converters

Current page: 1 of 4
Download datasheet (65Kb)

Errata

•

11. LDS/STS when Accessing External RAM

10. STS when Accessing EEPROM

9. COM1B Settings Never Disconnects OC1B

8. UART Loses Synchronization if RXD Line is Low when UART Receive is

LDS/STS when Accessing External RAM

STS when Accessing EEPROM

COM1B Settings Never Disconnects OC1B

UART Loses Synchronization if RXD Line is Low when UART Receive is Disabled

Releasing Reset Condition without Clock

Lock Bits at High V

The SPI Can Send Wrong Byte

Reset during EEPROM Write

SPI Interrupt Flag Can be Undefined after Reset

Serial Programming at Voltages below 3.0 Volts

Skip Instructions with Interrupts

Using an LDS instruction for reading external RAM corrupts the source register

used in the LDS instruction when directly followed by NOP. An STS instruction for

writing to external RAM corrupts R0 when directly followed by NOP.

Problem Fix/Workaround

Do not insert a NOP instruction directly after an LDS or STS instruction used for

accessing the external RAM.

If the STS instruction is used to start an EEPROM write (EEWE in EECR), the

following instruction may have an undesired result. In the case of NOP, R0

will be corrupted.

Problem Fix/Workaround

Use the OUT or SBI instruction to start an EEPROM write.

According to the datasheet, Timer/Counter1 should be disconnected from the

O C 1 B p i n w h e n C O M 1 B [ 1 : 0 ] = “ 0 0 ” i n n o n - P W M m o d e , a n d w h e n

COM1B[1:0] = “00” or “01” in PWM mode. This, however, is not the case.

For OC1A, the description in the datasheet is correct; the general digital I/O func-

tion takes over.

Problem Fix/Workaround

As OC1B is an output only pin with no general digital I/O function, the pin cannot

be tri-staded. However, if there is a need to stop the pin from toggling, disable the

PWM mode by setting PWM[1:0] to “00” and set the COM1A[1:0] to anything else

than “01” (which is the toggle mode). Warning: As long as the timer is still running,

the counter can count to a value above the maximum for that PWM mode. As an

alternative, the timer can be stopped by setting CS1[2:0] in TCCR1B to “000”.

Disabled

The UART will detect an UART start bit and start reception even if the UART is not

enabled. If this occurs, the first byte after reenabling the UART will be corrupted.

Problem Fix/Workaround

Make sure that the RX line is high at start-up and when the UART is disabled. An

external RS232-level converter keeps the line high during start-up.

8-bit

Microcontroller

with 8K Bytes

In-System

Programmable

Flash

AT90S8515

Rev. B

Errata Sheet

Rev. 1195E–09/01

Related parts for AT90S8515A-8PC

AT90S8515A-8PC Summary of contents

Page 1

Errata • LDS/STS when Accessing External RAM • STS when Accessing EEPROM • COM1B Settings Never Disconnects OC1B • UART Loses Synchronization if RXD Line is Low when UART Receive is Disabled • Releasing Reset Condition without Clock • Lock ...

Page 2

Releasing Reset Condition without Clock external reset or a watchdog reset occurs while the clock is stopped and the reset is released before the clock is restarted, the internal reset will time-out after the start-up delay which ...

Page 3

Skip Instruction with Interrupts A skip instruction (SBRS, SBRC, SBIS, SBIC, CPSE) that skips a 2-word instruction needs 3 clock cycles inter- rupt occurs during the first or second clock cycle of this skip instruction, the return ...

Page 4

... No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ...

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