PIC16C63-20E/SP Microchip Technology, PIC16C63-20E/SP Datasheet - Page 31

• Manufacturer Part Number: PIC16C63-20E/SP
• Description: IC MCU OTP 4KX14 PWM 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C63-20E/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• For Use With: DVMCPA - KIT DVR BOARD EVAL SYSTEM MXDEV1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

TABLE 4-5:
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.
Note 1: These registers can be addressed from either bank.
Address Name
Bank 1
1997 Microchip Technology Inc.
(1)
(1)
(1)
(1)
(1,2)
(1)
2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4: The BOR bit is reserved on the PIC16C65, always maintain this bit set.
5: The IRP and RP1 bits are reserved on the PIC16C65/65A/R65, always maintain these bits clear.
6: PIE1<6> and PIR1<6> are reserved on the PIC16C65/65A/R65, always maintain these bits clear.
INDF
OPTION
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
Shaded locations are unimplemented, read as ‘0’.
contents are transferred to the upper byte of the program counter. (PC<12:8>)
—
—
—
—
—
—
—
—
—
—
—
—
SPECIAL FUNCTION REGISTERS FOR THE PIC16C65/65A/R65 (Cont.’d)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
Unimplemented
Unimplemented
Unimplemented
Timer2 Period Register
Synchronous Serial Port (I
Unimplemented
Unimplemented
Unimplemented
Baud Rate Generator Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
PSPIE
RBPU
CSRC
IRP
Bit 7
IBF
GIE
—
—
—
—
—
(5)
INTEDG
RP1
PEIE
Bit 6
OBF
TX9
(6)
—
—
—
—
—
(5)
PORTA Data Direction Register
2
TXEN
T0CS
C mode) Address Register
IBOV
RCIE
Bit 5
T0IE
RP0
D/A
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
PSPMODE
SYNC
T0SE
INTE
Bit 4
TXIE
TO
—
—
P
SSPIE
RBIE
Bit 3
PSA
PD
—
—
—
—
S
PORTE Data Direction Bits
CCP1IE
BRGH
Bit 2
T0IF
R/W
PS2
—
—
Z
TMR2IE
TRMT
Bit 1
INTF
POR
PS1
DC
UA
—
TMR1IE
CCP2IE
BOR
TX9D
RBIF
Bit 0
PS0
BF
C
PIC16C6X
(4)
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
0000 -111 0000 -111
---0 0000 ---0 0000
0000 000x 0000 000u
0000 0000 0000 0000
---- ---0 ---- ---0
---- --qq ---- --uu
1111 1111 1111 1111
0000 0000 0000 0000
--00 0000 --00 0000
0000 -010 0000 -010
0000 0000 0000 0000
Value on:
POR,
BOR
DS30234D-page 31
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Value on
resets
all other
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—
—
—
—
—
—
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(3)