PIC17C43-25I/PT Microchip Technology, PIC17C43-25I/PT Datasheet - Page 223

• Manufacturer Part Number: PIC17C43-25I/PT
• Description: IC MCU OTP 4KX16 PWM 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C43-25I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: OTP
• Ram Size: 454 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• For Use With: AC164315 - MODULE SKT MPLAB PM3 44TQFP309-1008 - ADAPTER 44-TQFP TO 40-DIPAC174005 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

APPENDIX F: ERRATA FOR
The PIC17C42 devices that you have received have the
following anomalies. At present there is no intention for
future revisions to the present PIC17C42 silicon. If
these cause issues for the application, it is recom-
mended that you select the PIC17C42A device.
1.
a)
b)
EXAMPLE F-1:
LOOP
2.
a)
b)
1996 Microchip Technology Inc.
Note:
When the Oscillator Start-Up Timer (OST) is
enabled (in LF or XT oscillator modes), any inter-
rupt that wakes the processor may cause a WDT
reset. This occurs when the WDT is greater than
or equal to 50% time-out period when the SLEEP
instruction is executed. This will not occur in
either the EC or RC oscillator modes.
Work-arounds
Always ensure that the CLRWDT instruction is
executed before the WDT increments past 50%
of the WDT period. This will keep the “false”
WDT reset from occurring.
When using the WDT as a normal timer (WDT
disabled), ensure that the WDT is less than or
equal to 50% time-out period when the SLEEP
instruction is executed. This can be done by
monitoring the TO bit for changing state from set
to clear. Example 1 shows putting the PIC17C42
to sleep.
When the clock source of Timer1 or Timer2 is
selected to external clock, the overflow interrupt
flag will be set twice, once when the timer equals
the period, and again when the timer value is
reset to 0h. If the latency to clear TMRxIF is
greater than the time to the next clock pulse, no
problems will be noticed. If the latency is less
than the time to the next timer clock pulse, the
interrupt will be serviced twice.
Work-arounds
Ensure that the timer has rolled over to 0h before
clearing the flag bit.
Clear the timer in software. Clearing the timer in
software causes the period to be one count less
than expected.
BTFSS
CLRWDT
BTFSC
GOTO
SLEEP
New designs should use the PIC17C42A.
CPUSTA, TO
CPUSTA, TO
LOOP
PIC17C42 SILICON
PIC17C42 TO SLEEP
This document was created with FrameMaker 4 0 4
; TO = 0?
; YES, WDT = 0
; WDT rollover?
; NO, Wait
; YES, goto Sleep
Design considerations
The device must not be operated outside of the speci-
fied voltage range. An external reset circuit must be
used to ensure the device is in reset when a brown-out
occurs or the V
ensure that the device is in reset when device voltage
is out of specification may cause the device to lock-up
and ignore the MCLR pin.
DD
rise time is too long. Failure to
PIC17C4X
DS30412C-page 223