AT89LV51-12PI Atmel, AT89LV51-12PI Datasheet - Page 5

• Manufacturer Part Number: AT89LV51-12PI
• Description: IC MICRO CTRL 12MHZ 40DIP
• Manufacturer: Atmel
• Series: 89LVr

Specifications of AT89LV51-12PI

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: UART/USART
• Number Of I /o: 32
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Peripherals: -
• Other names: AT89LV5112PI

Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier which can be configured for use as
an on-chip oscillator, as shown in Figure 1. Either a quartz
crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven as shown in Figure 2.
There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry
is through a divide-by-two flip-flop, but minimum and maxi-
mum voltage high and low time specifications must be
observed
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-
chip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the spe-
cial functions registers remain unchanged during this
mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
It should be noted that when idle is terminated by a hard-
ware reset, the device normally resumes program execu-
tion, from where it left off, up to two machine cycles before
the internal reset algorithm takes control. On-chip hardware
inhibits access to internal RAM in this event, but access to
the port pins is not inhibited. To eliminate the possibility of
an unexpected write to a port pin when Idle is terminated by
reset, the instruction following the one that invokes Idle
should not be one that writes to a port pin or to external
memory.
Power Down Mode
In the power down mode the oscillator is stopped, and the
instruction that invokes power down is the last instruction
executed. The on-chip RAM and Special Function Regis-
ters retain their values until the power down mode is termi-
nated. The only exit from power down is a hardware reset.
Reset redefines the SFRs but does not change the on-chip
RAM. The reset should not be activated before V
restored to its normal operating level and must be held
active long enough to allow the oscillator to restart and sta-
bilize.
Status of External Pins During Idle and Power Down Modes
Mode
Idle
Idle
Power Down
Power Down
Program Memory
Internal
External
Internal
External
ALE
CC
1
1
0
0
is
PSEN
Figure 1. Oscillator Connections
Note:
Figure 2. External Clock Drive Configuration
1
1
0
0
C1, C2 = 30 pF ± 10 pF for Crystals
PORT0
Float
Float
Data
Data
OSCILLATOR
EXTERNAL
SIGNAL
= 40 pF ± 10 pF for Ceramic Resonators
NC
C2
C1
PORT1
Data
Data
Data
Data
XTAL2
XTAL1
GND
Address
PORT2
Data
Data
Data
XTAL2
XTAL1
GND
PORT3
Data
Data
Data
Data
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