PIC18F442T-E/L Microchip Technology, PIC18F442T-E/L Datasheet

IC MCU CMOS 40MHZ 8K FLSH 44PLCC

PIC18F442T-E/L

Manufacturer Part Number
PIC18F442T-E/L
Description
IC MCU CMOS 40MHZ 8K FLSH 44PLCC
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F442T-E/L

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-PLCC
For Use With
XLT44L2 - SOCKET TRAN ICE 44PLCCDVA16XL441 - ADAPTER DEVICE ICE 44PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
The PIC18FXX2 Rev. B3/B4 parts you have received
conform functionally to the Device Data Sheet
(DS39564B), except for the anomalies described
below.
All the issues listed here will be addressed in future
revisions of the PIC18FXX2 silicon.
The
PIC18FXX2 devices with these Device/Revision
IDs:
1. Module: Program Memory
© 2005 Microchip Technology Inc.
The Device IDs (DEVID1 and DEVID2) are located at
addresses
configuration space. They are shown in hexadecimal
in the format “DEVID2 DEVID1”.
Part Number
PIC18F242
PIC18F252
PIC18F442
PIC18F452
Data corruption may occur during a table write
operation if a peripheral interrupt also occurs. This
happens only when the interrupt enable bit (PIE or
INTCON register) for the corresponding interrupt
has also been set.
Work around
Before executing any table write instructions, dis-
able ALL peripheral interrupts. This is best done by
clearing all interrupt enable bits in the three Inter-
rupt Control registers (INTCON, INTCON2 and
INTCON3) and both Peripheral Interrupt Enable
registers (PIE1 and PIE2). After the table write is
complete, restore all INTCON and PIE registers to
their pre-instruction state.
Date Codes that pertain to this issue:
All engineering and production devices.
following
PIC18FXX2 Rev. B3/B4 Silicon/Data Sheet Errata
3FFFFEh:3FFFFFh
silicon
00 0100 100
00 0100 000
00 0100 101
00 0100 001
Device ID
errata apply
in
Revision ID
the
00101
00101
00101
00101
only
device’s
to
2. Module: Data EEPROM
EXAMPLE 1:
BCF
BSF
MOVF
BSF
When reading the data EEPROM, the contents of
the EEDATA register may become corrupted in the
second instruction cycle after the RD bit
(EECON1<0>) is set. The actual contents of the
EEPROM remains unaffected.
Work around
To ensure the integrity of the contents of EEDATA,
the register must be read in the instruction imme-
diately following the setting of the RD bit. Use the
MOVF or MOVFF instructions to do this (see
Example 1).
Additionally, all interrupts must be disabled prior to
the read instruction sequence. Interruptions of the
sequence may have the same result of altering the
contents of EEDATA.
Date Codes that pertain to this issue:
All engineering and production devices.
PIC18FXX2
INTCON,GIEH ;disable interrupts
EECON1,RD
EEDATA,W
INTCON,GIEH ;enable interrupts
SUGGESTED SEQUENCE
FOR READING EEDATA
;if using interrupts
;start the read operation
;move the data out of
;EEDATA
;if using interrupts
DS80127G-page 1

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PIC18F442T-E/L Summary of contents

Page 1

... INTCON and PIE registers to their pre-instruction state. Date Codes that pertain to this issue: All engineering and production devices. © 2005 Microchip Technology Inc. PIC18FXX2 2. Module: Data EEPROM When reading the data EEPROM, the contents of the EEDATA register may become corrupted in the second instruction cycle after the RD bit (EECON1< ...

Page 2

... This is a recommended solution. Others may exist. Date Codes that pertain to this issue: All engineering samples and devices with date codes up to and including 0252 (Year 2002, Work Week 52). © 2005 Microchip Technology Inc. over ID locations bytes ...

Page 3

... Date Codes that pertain to this issue: All engineering samples and devices with date codes up to and including 0252 (Year 2002, Work Week 52). © 2005 Microchip Technology Inc. PIC18FXX2 7. Module: Data EEPROM When reading the data EEPROM, the contents of the EEDATA register may be corrupted if the RD bit (EECON1< ...

Page 4

... Affected systems will repeatably fail normal testing. Systems not affected will continue to not be affected over time. Work around Insert a NOP instruction at address 0x0000. Date Codes that pertain to this issue: All engineering and production devices. © 2005 Microchip Technology Inc. ...

Page 5

... Sleep mode, with all I/O pins in hi-impedance state and tied to V features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR,...). 4: For RC osc configuration, current through R estimated by the formula © 2005 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) -40°C ≤ T Operating temperature Standard Operating Conditions (unless otherwise stated) -40° ...

Page 6

... Device Data Sheet. “MLF” should be considered an obsoleted term PIC18F442 PIC18F452 Example PIC18F442 -I/ML OSC2/CLKO/RA6 OSC1/CLKI RE2/AN7/CS RE1/AN6/WR RE0/AN5/RD RA5/AN4/SS/LVDIN RA4/T0CKI 0510017 © 2005 Microchip Technology Inc. ...

Page 7

... RA5 AN4 SS LVDIN RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output OD = Open Drain (no P diode to V © 2005 Microchip Technology Inc. Pin Buffer Type Type 18 Master Clear (input) or high voltage ICSP™ programming enable pin Master Clear (Reset) input. This pin is an active low Reset to the device ...

Page 8

... I/O TTL Digital I/O. Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming clock pin. 17 I/O TTL Digital I/O. Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power ) DD Description © 2005 Microchip Technology Inc. ...

Page 9

... TX CK RC7/RX/ RC7 RX DT Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output OD = Open Drain (no P diode to V © 2005 Microchip Technology Inc. Pin Buffer Type Type PORTC is a bidirectional I/O port. 32 I/O ST Digital I/O. O — Timer1 oscillator output. ...

Page 10

... Ground reference for logic and I/O pins — Positive supply for logic and I/O pins. 12, 13, — — These pins are not internally connected. They 33, 34 should be left unconnected. CMOS = CMOS compatible input or output I = Input P = Power ) DD Description © 2005 Microchip Technology Inc. ...

Page 11

... Parameter Notes: 1. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M 2. REF: Reference Dimension, usually without tolerance, for information purposes only. See ASME Y14.5M JEDEC equivalent: M0-220 Drawing No. C04-103 © 2005 Microchip Technology Inc. EXPOSED METAL PAD ...

Page 12

... Space). Added silicon issues 8, 9 and 10 (MSSP and Core - Instruction Set) and data sheet clarification 2 (Packaging - Pinout and Product Identification). Rev F Document (7/2003) Added silicon issue 11 (Timer1 Oscillator). Rev G Document (05/2005) Added silicon issue 12 (Reset). DS80127G-page 12 © 2005 Microchip Technology Inc. ...

Page 13

... PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 14

... Fax: 65-6334-8850 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Taiwan - Hsinchu Tel: 886-3-572-9526 Fax: 886-3-572-6459 © 2005 Microchip Technology Inc. EUROPE Austria - Weis Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Ballerup Tel: 45-4450-2828 Fax: 45-4485-2829 France - Massy Tel: 33-1-69-53-63-20 ...

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