ATMEGA162V-1PC Atmel, ATMEGA162V-1PC Datasheet - Page 249

• Manufacturer Part Number: ATMEGA162V-1PC
• Description: IC MCU AVR 16K 1.8V 8MHZ 40-DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162V-1PC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 1MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

AVR_RESET (0xC)
PROG_ENABLE (0x4)
PROG_COMMANDS (0x5)
PROG_PAGELOAD (0x6)
PROG_PAGEREAD (0x7)
2513C–AVR–09/02
The AVR specific public JTAG instruction for setting the AVR device in the Reset mode
or taking the device out from the Reset mode. The TAP controller is not reset by this
instruction. The one bit Reset Register is selected as data register. Note that the reset
will be active as long as there is a logic “one” in the Reset Chain. The output from this
chain is not latched.
The active states are:
•
The AVR specific public JTAG instruction for enabling programming via the JTAG port.
The 16-bit Programming Enable Register is selected as data register. The active states
are the following:
•
•
The AVR specific public JTAG instruction for entering programming commands via the
JTAG port. The 15-bit Programming Command Register is selected as data register.
The active states are the following:
•
•
•
•
The AVR specific public JTAG instruction to directly load the Flash data page via the
JTAG port. The 1024 bit Virtual Flash Page Load Register is selected as register. This is
a virtual scan chain with length equal to the number of bits in one Flash page. Internally
the Shift Register is 8-bit. Unlike most JTAG instructions, the Update-DR state is not
used to transfer data from the Shift Register. The data are automatically transferred to
the Flash page buffer byte-by-byte in the Shift-DR state by an internal state machine.
This is the only active state:
•
The AVR specific public JTAG instruction to read one full Flash data page via the JTAG
port. The 1032 bit Virtual Flash Page Read Register is selected as data register. This is
a virtual scan chain with length equal to the number of bits in one Flash page plus eight.
Internally the Shift Register is 8-bit. Unlike most JTAG instructions, the Capture-DR
state is not used to transfer data to the Shift Register. The data are automatically trans-
ferred from the Flash page buffer byte-by-byte in the Shift-DR state by an internal state
machine. This is the only active state:
•
Note:
Shift-DR: The Reset Register is shifted by the TCK input.
Shift-DR: The programming enable signature is shifted into the Data Register.
Update-DR: The programming enable signature is compared to the correct value,
and Programming mode is entered if the signature is valid.
Capture-DR: The result of the previous command is loaded into the Data Register.
Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the
previous command and shifting in the new command.
Update-DR: The programming command is applied to the Flash inputs.
Run-Test/Idle: One clock cycle is generated, executing the applied command (not
always required, see Table 112 below).
Shift-DR: Flash page data are shifted in from TDI by the TCK input, and
automatically loaded into the Flash page one byte at a time.
Shift-DR: Flash data are automatically read one byte at a time and shifted out on
TDO by the TCK input. The TDI input is ignored.
The JTAG instructions PROG_PAGELOAD and PROG_PAGEREAD can only be used if
the AVR devce is the first decive in JTAG scan chain. If the AVR cannot be the first
device in the scan chain, the byte-wise programming algorithm must be used.
ATmega162(V/U/L)
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