AT91FR40162S-CJ Atmel, AT91FR40162S-CJ Datasheet
AT91FR40162S-CJ
Specifications of AT91FR40162S-CJ
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AT91FR40162S-CJ Summary of contents
Page 1
... Available in a 121-ball 1.2 mm BGA Package with 0.8 mm Ball Pitch 1. Description The AT91FR40162S is a member of the Atmel AT91 16/32-bit Microcontroller family, which is based on the ARM7TDMI processor core. The processor has a high-perfor- mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption ...
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... Pin Configuration Figure 2-1. AT91FR40162S Pinout for 121-ball BGA Package (Top View) A1 Corner 1 2 P21/TXD1 P19 NTRI P22 P20 RXD1 SCK1 VDDIO GND P23 MCKI P24 P25 NWDOVF BMS MCK0 GND TMS NWE TDO NWR0 P26 VDDCORE VDDIO NCS2 NWAIT GND ...
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... Signal Description Table 3-1. AT91FR40162S Signal Description Module Name Function A0 - A23 Address Bus D0 - D15 Data Bus NCS0 - NCS3 External Chip Select CS4 - CS7 External Chip Select NWR0 Lower Byte 0 Write Signal NWR1 Upper Byte 1 Write Signal NRD Read Signal EBI NWE ...
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... Table 3-1. AT91FR40162S Signal Description (Continued) Module Name Function NCSF Flash Memory Select Flash NBUSY Flash Memory Busy Output Memory NRSTF Flash Memory Reset Input VDDIO Power VDDCORE Power Power GND Ground VPP Write Protection AT91FR40162S Preliminary 4 Active Type Level Comments ...
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... Block Diagram Figure 4-1. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary AT91FR40162S Interface Bus External EBI: 5 ...
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... Memories The AT91FR40162S embeds 256K bytes of internal SRAM. The internal memory is directly con- nected to the 32-bit data bus and is single-cycle accessible. This provides maximum performance of 67 MIPS at 75 MHz by using the ARM instruction set of the processor, minimiz- ing system power consumption and improving on the performance of separate memory solutions ...
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... The 3-channel, 16-bit Timer Counter (TC) is highly programmable and supports capture or waveform modes. Each TC channel can be programmed to measure or generate different kinds of waves, and can detect and control two input/output signals. The TC has also 3 external clock signals. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary 7 ...
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... Master Clock The AT91FR40162S has a fully static design and works on the Master Clock (MCK), provided on the MCKI pin from an external source. The Master Clock is also provided as an output of the device on the pin MCKO, which is multi- plexed with a general purpose I/O line ...
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... Tri-state Mode The AT91FR40162S microcontroller provides a tri-state mode, which is used for debug pur- poses. This enables the connection of an emulator probe to an application board without having to desolder the device from the target board. In tri-state mode, all the output pin drivers of the AT91R40008 microcontroller are disabled ...
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... In any of these address spaces, the ARM7TDMI operates in little-endian mode only. 6.6.1 Internal Memories The AT91FR40162S microcontroller integrates 256K bytes of internal SRAM bits wide and single-clock cycle accessible. Byte (8-bit), half-word (16-bit) and word (32-bit) accesses are supported and are executed within one cycle. Fetching either Thumb or ARM instructions is sup- ported, and internal memory can store two times as many Thumb instructions as ARM instructions ...
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... The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt, Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to allow these vectors to be redefined dynamically by the software, the AT91FR40162S uses a remap command that enables switching between the boot memory and the internal primary SRAM bank addresses. ...
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... Program Inhibit – holding any one of OE low, CE high or WE high inhibits program cycles. • Noise Filter – pulses of less than a certain duration on the inputs will not initiate a program cycle. AT91FR40162S Preliminary 12 6174B–ATARM–07-Nov-05 ...
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... Flash Memory Uploader Operations The Flash Memory Uploader requires the encapsulated Flash to be used as the AT91FR40162S boot memory and a valid clock to be applied to MCKI. After reset, the Flash Memory Uploader immediately recopies itself into the internal SRAM and jumps to it. The following operation requires this memory resource only ...
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... Note that in the event that the Flash Memory Uploader is erased from the first sector while the new final application is not yet programmed, and while the target system power supply is switched off, it leads to a non-recoverable error and the AT91FR40162S cannot be re-pro- grammed by using the Flash Memory Uploader. ...
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... Peripheral Data Controller The AT91FR40162S has a 4-channel PDC dedicated to the two on-chip USARTs. One PDC channel is dedicated to the receiver and one to the transmitter of each USART. The user interface of a PDC channel is integrated in the memory space of each USART. It con- tains a 32-bit Address Pointer Register (RPR or TPR) and a 16-bit Transfer Counter Register (RCR or TCR) ...
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... PIO: Parallel I/O Controller The AT91FR40162S has 32 programmable I/O lines. Six pins are dedicated as general-purpose I/O pins. Other I/O lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins. The PIO controller enables generation of an interrupt on input change and insertion of a simple input glitch filter on any of the PIO pins ...
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... TC: Timer Counter The AT91FR40162S features a Timer Counter block that includes three identical 16-bit timer counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse gen- eration, delay timing and pulse width modulation. ...
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... Memory Map Figure 8-1. AT91FR40162S Memory Map Before and After the Remap Command Before Address Function Size 0xFFFFFFFF On-chip 4M Bytes Peripherals 0xFFC00000 0xFFBFFFFF Reserved 0x00400000 0x003FFFFF On-chip 1M Byte Primary RAM Bank 0x00300000 0x002FFFFF Reserved 1M Byte On-chip Device 0x00200000 0x001FFFFF Reserved 1M Byte ...
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... AT91FR40162S Preliminary Peripheral Peripheral Name AIC Advanced Interrupt Controller Reserved WD WatchdogTimer PS Power Saving PIO Parallel I/O Controller Reserved Timer Counter TC Reserved Universal Synchronous/ ...
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... If two chip selects are defined as having the same base address, an access to the overlapping address space asserts both NCS lines. The Chip Select Register with the smaller number defines the characteristics of the external access and the behavior of the control signals. AT91FR40162S Preliminary 20 describes the EBI User Interface. ...
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... Upper and lower byte select (output) Wait request (input) Functions Allows from chip select lines to be used 8- or 16-bit data bus Byte write or byte select access Byte write or byte select access Byte write or byte select access AT91FR40162S Preliminary Base + 4M Bytes Hi Low Base + 3M Bytes Hi Low Base + 2M Bytes ...
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... Note: Figure 10-3. Memory Connections for Eight External Devices CS4 - CS7 NCS0 - NCS3 NRD EBI NWRx A0 - A19 D0 - D15 Note: AT91FR40162S Preliminary 22 NCS0 - NCS3 NRD NWRx A0 - A23 D0 - D15 For four external devices, the maximum address space per device is 16M bytes. NCS1 NCS0 For eight external devices, the maximum address space per device is 1M byte ...
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... DBW field in the EBI_CSR (Chip Select Register) for the corresponding chip select. Figure 10-4 Figure 10-4. Memory Connection for an 8-bit Data Bus Figure 10-5 Figure 10-5. Memory Connection for a 16-bit Data Bus 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary shows how to connect a 512K x 8-bit memory on NCS2 D15 A1 - A18 EBI ...
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... The signal NWR1/NUB is used as NUB and enables the upper byte for both read and write operations. • The signal NWR0/NWE is used as NWE and enables writing for byte or half word. • The signal NRD/NOE is used as NOE and enables reading for byte or half word. AT91FR40162S Preliminary 24 shows how to connect two 512K x 8-bit devices in parallel on NCS2 ...
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... Figure 10-7. Connection for a 16-bit Data Bus with Byte and Half-word Access Figure 10-8 Figure 10-8. Connection for a 16-bit Data Bus without Byte Write Capability. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary shows how to connect a 16-bit device with byte and half-word access (e.g. 16-bit D15 ...
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... AT91FR40162S Preliminary 26 In the following waveforms and descriptions, NRD represents NRD and NOE since the two signals have the same waveform ...
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... Early read wait states affect the external bus only. They do not affect internal bus timing. Figure 10-9. Standard Read Protocol Figure 10-10. Early Read Protocol 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary MCKI ADDR NCS NRD ...
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... Figure 10-12. Data Hold Time In early read protocol the data can remain valid longer than in standard read protocol due to the additional wait cycle which follows a write access. AT91FR40162S Preliminary 28 Write Cycle Early Read Wait ...
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... Section 10.7 ”Read Protocols”, on page 1/2 cycle 1 cycle 1 Wait State Access MCK ADDR NCS NWE NRD (2) (1) 1. Early Read Protocol 2. Standard Read Protocol ) for each external memory device is programmed in the TDF DF AT91FR40162S Preliminary 26) 29 ...
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... When NWAIT is de-asserted, the EBI finishes the access sequence. The NWAIT signal must meet setup and hold requirements on the rising edge of the clock. AT91FR40162S Preliminary 30 will not slow down the execution of a program from internal ...
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... Figure 10-16. Chip Select Wait Notes: 6174B–ATARM–07-Nov-05 MCK ADDR NWAIT NCS NWE NRD (2) (1) 1. Early Read Protocol 2. Standard Read Protocol Mem 1 MCK NCS1 NCS2 NRD (1) (2) NWE 1. Early Read Protocol 2. Standard Read Protocol AT91FR40162S Preliminary Chip Select Wait Mem 2 31 ...
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... Memory Access Waveforms Figure 10-17 memory read access. Figure 10-17. Standard Read Protocol without t AT91FR40162S Preliminary 32 through Figure 10-20 show examples of the two alternative protocols for external DF 6174B–ATARM–07-Nov-05 ...
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... Figure 10-18. Early Read Protocol Without t 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary DF 33 ...
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... Figure 10-19. Standard Read Protocol with t AT91FR40162S Preliminary 34 DF 6174B–ATARM–07-Nov-05 ...
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... Figure 10-20. Early Read Protocol With t 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary DF 35 ...
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... Figure 10-21 access to the various AT91FR40162S external memory devices. The configurations described are shown in the following table: Table 10-3. Figure Number Figure 10-21 Figure 10-22 Figure 10-23 Figure 10-24 Figure 10-25 Figure 10-26 Figure 10-27 AT91FR40162S Preliminary 36 through Figure 10-27 show the timing cycles and wait states for read and write ...
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... Figure 10-21. 0 Wait States, 16-bit Bus Width, Word Transfer MCK A1 - A23 NCS NLB NUB READ ACCESS · Standard Protocol NRD D0 - D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS · Byte Write/ Byte Select Option NWE D0 - D15 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary ADDR ADDR ...
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... Figure 10-22. 1 Wait, 16-bit Bus Width, Word Transfer MCK A1 - A23 NCS NLB NUB READ ACCESS · Standard Protocol NRD D0 - D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS · Byte Write/ Byte Select Option NWE D0 - D15 AT91FR40162S Preliminary 38 1 Wait State ADDR Wair State ADDR ...
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... Figure 10-23. 1 Wait State, 16-bit Bus Width, Half-word Transfer MCK A1 - A23 READ ACCESS · Standard Protocol D0 - D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS · Byte Write/ Byte Select Option NWE D0 - D15 6174B–ATARM–07-Nov-05 1 Wait State NCS NLB NUB NRD AT91FR40162S Preliminary ...
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... Figure 10-24. 0 Wait States, 8-bit Bus Width, Word Transfer MCK A0 - A23 NCS READ ACCESS · Standard Protocol NRD D0-D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS NWR0 NWR1 D0 - D15 AT91FR40162S Preliminary 40 ADDR ADDR ADDR+2 ADDR 6174B–ATARM–07-Nov- ...
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... Figure 10-25. 1 Wait State, 8-bit Bus Width, Half-word Transfer 1 Wait State MCK A0 - A23 NCS READ ACCESS · Standard Protocol NRD D0 - D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS NWR0 NWR1 D0 - D15 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary 1 Wait State ADDR ADDR ...
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... Figure 10-26. 1 Wait State, 8-bit Bus Width, Byte Transfer MCK A0 - A23 NCS READ ACCESS · Standard Protocol NRD D0 - D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS NWR0 NWR1 D0 - D15 AT91FR40162S Preliminary 42 1 Wait State 6174B–ATARM–07-Nov-05 ...
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... Internal Address NCS NLB NUB READ ACCESS · Standard Protocol NRD D0 - D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS · Byte Write Option NWR0 NWR1 D0 - D15 · Byte Select Option NWE 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary ADDR ADDR ADDR ADDR ...
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... Chip Select Register 6 0x1C Chip Select Register 7 0x20 Remap Control Register 0x24 Memory Control Register Notes: 1. 8-bit boot (if BMS is detected high) 2. 16-bit boot (if BMS is detected low) AT91FR40162S Preliminary 44 (See “Boot on NCS0” on page Name Access EBI_CSR0 Read/Write EBI_CSR1 Read/Write EBI_CSR2 Read/Write ...
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... CSEN BAT 5 4 WSE NWS Data Bus Width Reserved 16-bit data bus width 8-bit data bus width Reserved Number of Standard Wait States AT91FR40162S Preliminary – – – TDF Code Label EBI_DBW – EBI_DBW_16 EBI_DBW_8 – Code Label EBI_NWS EBI_NWS_1 EBI_NWS_2 EBI_NWS_3 ...
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... Chip select is enabled. • BA: Base Address (Code Label EBI_BA) These bits contain the highest bits of the base address. If the page size is larger than 1M byte, the unused bits of the base address are ignored by the EBI decoder. AT91FR40162S Preliminary 46 Active Bits in Base Address 12 Bits (31 - 20) ...
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... RCB: Remap Command Bit (Code Label EBI_RCB effect Cancels the remapping (performed at reset) of the page zero memory devices. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary – – – – – – – – – ...
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... A20, A21 A20 None • DRP: Data Read Protocol DRP Selected DRP 0 Standard read protocol for all external memory devices enabled 1 Early read protocol for all external memory devices enabled AT91FR40162S Preliminary – – – – – – – – ...
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... I/O7 are active and controlled by CE and OE. The data I/O pins I/O8 - I/O14 are tri-stated, and the I/O15 pin is used as an input for the LSB (A-1) address function. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary ”Sector Lockdown” on page 53). input is below 0.4V, the program and erase ...
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... low (respectively) and OE high. The address is latched on the falling edge WE, whichever occurs last. The data is latched by the first rising edge WE. Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences. AT91FR40162S Preliminary 50 I/O0 - I/O15/A-1 Output ...
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... The circuitry of the Flash is designed so that the device cannot be programmed or erased if the V voltage is less that 0.4V. When V PP tions can be performed. The VPP pin cannot be left floating. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary . When the sector programming lockdown feature is not SEC is at 0.9V or above, normal program and erase opera ...
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... Please see details. The toggle bit status bit should be used in conjunction with the erase/program and V as shown in the algorithm in AT91FR40162S Preliminary 52 ”Status Bit Table” on page 60 Table 11-2, “Command Definition Table,” on page Table 11-1 on page 60 ...
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... Please see PP for more details. and Section 11.9 ”Software Product Identification Exit”, on page AT91FR40162S Preliminary ”Status Bit Table” on page 60 ”Status Bit Table” on Section 11.8 ”Software Product for more details. 64), a read ...
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... Product ID Exit command must be given prior to performing any other operation. 11.3.7 RDY/BUSY An open-drain READY/BUSY output pin provides another method of detecting the end of a pro- gram or erase operation. RDY/BUSY is actively pulled low during the internal program and erase AT91FR40162S Preliminary 54 “Software Product Identification Entry” 64. and ” ...
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... V CC power-on delay: once V CC power-on delay: once V has reached 1.65V, program and erase operations are PP PP AT91FR40162S Preliminary Table 11-1, “Status Bit Table,” below 1.8V (typical), the program function is CC has reached the V sense level, the device will ...
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... Figure 11-2. Data Polling Algorithm (Configuration Register = 00) Notes: AT91FR40162S Preliminary 56 START Read I/O7 - I/O0 Addr = VA I/O7 = Data I/O3, I/ YES Read I/O7 - I/O0 Addr = VA I/O7 = Data? NO Program/Erase Operation Not Successful, Write Product ID Exit Command Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased ...
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... VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non- protected sector address. 2. I/O7 should be rechecked even if I/O5 = “1” because I/O7 may change simultaneously with I/O5. AT91FR40162S Preliminary YES YES Program/Erase Operation ...
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... Figure 11-4. Toggle Bit Algorithm (Configuration Register = 00) Note: AT91FR40162S Preliminary 58 START Read I/O7 - I/O0 Read I/O7 - I/O0 Toggle Bit = Toggle? YES NO I/O3, I/ YES Read I/O7 - I/O0 Twice Toggle Bit = Toggle? YES Program/Erase Operation Not Successful, Write Product ID Exit Command The system should recheck the toggle bit even if I/O5 = “1” because the toggle bit may stop tog- gling as I/O5 changes to “ ...
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... Program/Erase Operation Not Successful, Write Product ID Exit Command The system should recheck the toggle bit even if I/O5 = “1” because the toggle bit may stop tog- gling as I/O5 changes to “1”. AT91FR40162S Preliminary NO NO Program/Erase Operation Successful, Write Product ID Exit Command ...
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... DATA Non-programming Sector Notes: 1. I/O5 switches to a “1” when a program or an erase operation has exceeded the maximum time limits or when a program or sector erase operation is performed on a protected sector. 2. I/O3 switches to a “1” when the V AT91FR40162S Preliminary 60 I/O7 I/O6 01 00/01 ...
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... Bytes of data other than F0 may be used to exit the Product ID mode. However recommended that F0 be used. 9. This fast programming option enables the user to program two words in parallel only when V and Addr2, of the two words, D turing purposes only. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary 2nd Bus 3rd Bus Cycle Cycle ...
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... Protection Register Addressing Table 11-3. Protection Register Addressing Table Word Use Block 0 Factory 1 Factory 2 Factory 3 Factory 4 User 5 User 6 User 7 User Note: 1. All address lines not specified in the above table must be “0” when accessing the protection register, i.e., A19 - AT91FR40162S Preliminary 62 ( ...
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... SA33 64K/32K SA34 64K/32K SA35 64K/32K SA36 64K/32K SA37 64K/32K SA38 64K/32K 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary x8 Address Range (A19 - A-1) 000000 - 001FFF 002000 - 003FFF 004000 - 005FFF 006000 - 007FFF 008000 - 009FFF 00A000 - 00BFFF 00C000 - 00DFFF 00E000 - 00FFFF 010000 - 01FFFF 020000 - 02FFFF ...
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... IL 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 001FH Device Code: 00C0H 6. Either one of the Product ID Exit commands can be used. AT91FR40162S Preliminary 64 Software Product Identification Entry LOAD DATA AA TO ADDRESS 555 ...
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... ADDRESS 555 LOAD DATA 55 ADDRESS AAA LOAD DATA 60 SECTOR ADDRESS PAUSE 200 s 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex) Address Format: A11 - A0 (Hex), A-1, and A11 - A19 (Don’t Care). 2. Sector Lockdown feature enabled. AT91FR40162S Preliminary ( (2) 65 ...
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... AT91FR40162S Preliminary 66 Data Comments 0051h “Q” 0052h “R” 0059h “Y” 0002h 0000h 0041h 0000h 0000h 0000h 0000h 0000h 0027h ...
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... AT91FR40162S Preliminary Data Comments Vendor Specific Extended Query 0050h “P” 0052h “R” 0049h “I” 0031h Major version number, ASCII 0030h Minor version number, ASCII Bit 0 – ...
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... Idle Mode. 12.1 Peripheral Clocks The clock of each peripheral integrated in the AT91FR40162S can be individually enabled and disabled by writing to the Peripheral Clock Enable (PS_PCER) and Peripheral Clock Disable Registers (PS_PCDR). The status of the peripheral clocks can be read in the Peripheral Clock Status Register (PS_PCSR) ...
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... Table 12-1. PS Memory Map Offset Register 0x00 Control Register 0x04 Peripheral Clock Enable Register 0x08 Peripheral Clock Disable Register 0x0C Peripheral Clock Status Register 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary Name Access PS_CR Write-only PS_PCER Write-only PS_PCDR Write-only PS_PCSR Read-only Reset State – ...
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... CPU: CPU Clock Disable effect Disables the CPU clock. The CPU clock is re-enabled by any enabled interrupt or by hardware reset. AT91FR40162S Preliminary – – – – – – – – – 5 ...
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... TC1: Timer Counter 1 Clock Enable effect Enables the Timer Counter 1 clock. • TC2: Timer Counter 2 Clock Enable effect Enables the Timer Counter 2 clock. • PIO: Parallel IO Clock Enable effect Enables the Parallel IO clock. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary – – – – ...
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... Disables the Timer Counter 0 clock. • TC1: Timer Counter 1 Clock Disable effect Disables the Timer Counter 1 clock. • TC2: Timer Counter 2 Clock Disable effect Disables the Timer Counter 2 clock. • PIO: Parallel IO Clock Disable effect Disables the Parallel IO clock. AT91FR40162S Preliminary – – – – ...
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... Timer Counter 1 clock is disabled Timer Counter 1 clock is enabled. • TC2: Timer Counter 2 Clock Status 0 = Timer Counter 2 clock is disabled Timer Counter 2 clock is enabled. • PIO: Parallel IO Clock Status 0 = Parallel IO clock is disabled Parallel IO clock is enabled. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary – – – – ...
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... AIC: Advanced Interrupt Controller The AT91FR40162S has an 8-level priority, individually maskable, vectored interrupt controller. This feature substantially reduces the software and real-time overhead in handling internal and external interrupts. The interrupt controller is connected to the NFIQ (fast interrupt request) and the NIRQ (standard interrupt request) inputs of the ARM7TDMI processor. The processor’ ...
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... Note: Reserved interrupt sources are not available. Corresponding registers must not be used and read 0. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary Interrupt Description FIQ Fast Interrupt SWIRQ Software Interrupt US0IRQ USART Channel 0 interrupt US1IRQ USART Channel 1 interrupt TC0IRQ Timer Channel 0 interrupt TC1IRQ Timer Channel 1 interrupt ...
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... This permits the AIC to assert the NIRQ line again when a higher priority unmasked interrupt occurs. At the end of the interrupt service routine, the end of interrupt command register (AIC_EOICR) must be written. This allows pending interrupts to be serviced. AT91FR40162S Preliminary 76 PC,[PC,# - &F20] Table 13-1 on page 75). 6174B– ...
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... With any sources programmed to be level sensitive, if the interrupt signal of the AIC input is de-asserted at the same time taken into account by the ARM7TDMI. • interrupt is asserted at the same time as the software is disabling the corresponding source through AIC_IDCR (this can happen due to the pipelining of the ARM core). 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary PC,[PC,# -&F20] 77 ...
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... The debug system must not write to the AIC_IVR as this would cause undesirable effects. The following table shows the main steps of an interrupt and the order in which they are per- formed according to the mode: AT91FR40162S Preliminary 78 111). 6174B–ATARM–07-Nov-05 ...
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... During this phase, an interrupt of priority higher than the current level will restart the sequence from step 1. Note that if the interrupt is 6174B–ATARM–07-Nov-05 level is the priority level of the current interrupt. must be read in order to de-assert NIRQ) AT91FR40162S Preliminary Normal Mode Read AIC_IVR Read AIC_IVR Read AIC_IVR ...
Page 80
... NFIQ line. 6. Finally, the Link Register (r14_fiq) is restored into the PC after decrementing (with instruction sub pc, lr, #4 for example). This has effect of returning from the inter- AT91FR40162S Preliminary 80 The I bit in the SPSR is significant set, it indicates that the ARM core was just about to mask IRQ interrupts when the mask instruction was interrupted ...
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... SPSR. The F bit in the SPSR is significant set, it indicates that the ARM core was just about to mask FIQ interrupts when the mask instruction was interrupted. Hence when the SPSR is restored, the interrupted instruction is completed (FIQ is masked). 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary 81 ...
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... Interrupt Set Command Register 0x130 End of Interrupt Command Register 0x134 Spurious Vector Register Note: 1. The reset value of this register depends on the level of the External IRQ lines. All other sources are cleared at reset. AT91FR40162S Preliminary 82 Name AIC_SMR0 AIC_SMR1 – AIC_SMR31 AIC_SVR0 AIC_SVR1 – ...
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... External Sources 0 0 Low Level Sensitive 0 1 Negative Edge Triggered 1 0 High Level Sensitive 1 1 Positive Edge Triggered SRCTYPE Internal Sources x 0 Level Sensitive x 1 Edge Triggered 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary – – – – – – – – – – ...
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... The IRQ Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt. The Source Vector Register (1 to 31) is indexed using the current interrupt number when the Interrupt Vector Register is read. When there is no current interrupt, the IRQ Vector Register reads 0. AT91FR40162S Preliminary ...
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... Offset: 0x108 31 30 – – – – – – – – • IRQID: Current IRQ Identifier (Code Label AIC_IRQID) The Interrupt Status Register returns the current interrupt source number. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary FIQV FIQV FIQV FIQV – – – ...
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... Register Name: AIC_IMR Access Type: Read-only Reset Value: 0 Offset: 0x110 31 30 – – – – – – WDIRQ TC2IRQ • Interrupt Mask 0 = Corresponding interrupt is disabled Corresponding interrupt is enabled. AT91FR40162S Preliminary – – – – – – – – – TC1IRQ TC0IRQ US1IRQ 29 ...
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... TC1IRQ TC0IRQ US1IRQ AT91FR40162S Preliminary 26 25 – – – – – – – NIRQ 26 25 – – IRQ2 IRQ1 10 9 – – US0IRQ SWIRQ 24 – ...
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... AIC Interrupt Clear Command Register Register Name: AIC_ICCR Access Type: Write-only Offset: 0x128 31 30 – – – – – – WDIRQ TC2IRQ • Interrupt Clear effect Clears corresponding interrupt. AT91FR40162S Preliminary – – – – – – – – – TC1IRQ TC0IRQ US1IRQ ...
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... TC1IRQ TC0IRQ US1IRQ – – – – – – – – – – – – AT91FR40162S Preliminary 26 25 – – IRQ2 IRQ1 10 9 – – US0IRQ SWIRQ 26 25 – – – – – – – – 24 – ...
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... AIC Spurious Vector Register Register Name: AIC_SPU Access Type: Read/Write Reset Value: 0 Offset: 0x134 • SPUVEC: Spurious Interrupt Vector Handler Address The user may store the address of the spurious interrupt handler in this register. AT91FR40162S Preliminary SPUVEC SPUVEC SPUVEC SPUVEC 26 25 ...
Page 91
... PIO: Parallel I/O Controller The AT91FR40162S has 32 programmable I/O lines. Six pins are dedicated as general purpose I/O pins (P16, P17, P18, P19, P23 and P24). Other I/O lines are multiplexed with an external sig- nal of a peripheral to optimize the use of available package pins (see The PIO controller also provides an internal interrupt signal to the Advanced Interrupt Controller ...
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... User Interface Each individual I/O is associated with a bit position in the Parallel I/O user interface registers. Each of these registers are 32 bits wide parallel I/O line is not defined, writing to the corre- sponding bits has no effect. Undefined bits read zero. AT91FR40162S Preliminary 92 6174B–ATARM–07-Nov-05 ...
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... Figure 14-1. Parallel I/O Multiplexed with a Bi-directional Signal Pad Output Enable Pad Output Pad Pad Input 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary PIO_OSR 1 0 PIO_PSR PIO_PSR PIO_PDSR Event Detection PIO_ISR PIO_IMR Peripheral Output Enable PIO_ODSR Peripheral Output Peripheral Input PIOIRQ 93 ...
Page 94
... P29 A21/CS6 30 P30 A22/CS5 31 P31 A23/CS4 Note: 1. Bit Number refers to the data bit that corresponds to this signal in each of the User Interface registers. AT91FR40162S Preliminary 94 Peripheral Signal Description Timer 0 Clock signal Timer 0 Signal A Timer 0 Signal B Timer 1 Clock signal Timer 1 Signal A Timer 1 Signal B ...
Page 95
... The reset value of this register depends on the level of the external pins at reset. 2. This register is cleared at reset. However, the first read of the register can give a value not equal to zero if any changes have occurred on any pins between the reset and the read. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary Name PIO_PER PIO_PDR PIO_PSR – ...
Page 96
... P15 P14 This register is used to disable PIO control of individual pins. When the PIO control is disabled, the normal peripheral func- tion is enabled on the corresponding pin Disables PIO control (enables peripheral control) on the corresponding pin effect. AT91FR40162S Preliminary P29 P28 P27 P21 ...
Page 97
... P6 This register is used to enable PIO output drivers. If the pin is driven by a peripheral, this has no effect on the pin, but the information is stored. The register is programmed as follows Enables the PIO output on the corresponding pin effect. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary P29 P28 P27 ...
Page 98
... This register shows the PIO pin control (output enable) status which is programmed in PIO_OER and PIO ODR. The defined value is effective only if the pin is controlled by the PIO. The register reads as follows The corresponding PIO is output on this line The corresponding PIO is input on this line. AT91FR40162S Preliminary ...
Page 99
... P15 P14 This register is used to disable input glitch filters. It affects the pin whether or not the PIO is enabled. The register is pro- grammed as follows Disables the glitch filter on the corresponding pin effect. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary P29 P28 P27 P21 P20 P19 ...
Page 100
... P7 P6 This register is used to set PIO output data. It affects the pin only if the corresponding PIO output line is enabled and if the pin is controlled by the PIO. Otherwise, the information is stored PIO output data on the corresponding pin is set effect. AT91FR40162S Preliminary 100 P29 P28 ...
Page 101
... This register shows the output data status which is programmed in PIO_SODR or PIO_CODR. The defined value is effec- tive only if the pin is controlled by the PIO Controller and only if the pin is defined as an output The output data for the corresponding line is programmed The output data for the corresponding line is programmed to 0. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary P29 ...
Page 102
... P23 P22 15 14 P15 P14 This register is used to enable PIO interrupts on the corresponding pin. It has effect whether PIO is enabled or not Enables an interrupt when a change of logic level is detected on the corresponding pin effect. AT91FR40162S Preliminary 102 P29 P28 P27 P21 P20 P19 13 ...
Page 103
... P15 P14 This register shows which pins have interrupts enabled updated when interrupts are enabled or disabled by writing to PIO_IER or PIO_IDR Interrupt is enabled on the corresponding input pin Interrupt is not enabled on the corresponding input pin. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary P29 P28 P27 P21 ...
Page 104
... PIO is selected for the pin or not and whether the pin is an input or output. The register is reset to zero following a read, and at reset least one change has been detected on the corresponding pin since the register was last read change has been detected on the corresponding pin since the register was last read. AT91FR40162S Preliminary 104 29 28 ...
Page 105
... WD: Watchdog Timer The AT91FR40162S has an internal watchdog timer which can be used to prevent system lock the software becomes trapped in a deadlock. In normal operation the user reloads the watchdog at regular intervals before the timer overflow occurs overflow does occur, the watchdog timer generates one or a combination of the following signals, depending on the parameters in WD_OMR (Overflow Mode Register): • ...
Page 106
... This step is unnecessary if the WD is already disabled (reset state). 2. Initialize the WD Clock Mode Register: Write 0x373C to WD_CMR (HPCV = 15 and WDCLKS = MCK/8) 3. Restart the timer: Write 0xC071 to WD_CR 4. Enable the watchdog: Write 0x2345 to WD_OMR (interrupt enabled) AT91FR40162S Preliminary 106 6174B–ATARM–07-Nov-05 ...
Page 107
... WD Base Address: 0xFFFF8000 (Code Label WD_BASE) Table 15-1. WD Memory Map Offset Register 0x00 Overflow Mode Register 0x04 Clock Mode Register 0x08 Control Register 0x0C Status Register 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary Name Access WD_OMR Read/Write WD_CMR Read/Write WD_CR Write-only WD_SR Read-only Reset State 0 0 – ...
Page 108
... Generation of a pulse on the pin NWDOVF by the Watch Dog is disabled When an overflow occurs, a pulse on the pin NWDOVF is generated. • OKEY: Overflow Access Key (Code Label WD_OKEY) Used only when writing WD_OMR. OKEY is read as 0. 0x234 = Write access in WD_OMR is allowed. Other value = Write access in WD_OMR is prohibited. AT91FR40162S Preliminary 108 – ...
Page 109
... Counter is preloaded when watchdog counter is restarted with bits set (FFF) and bits equaling HPCV. • CKEY: Clock Access Key (Code Label WD_CKEY) Used only when writing WD_CMR. CKEY is read as 0. 0x06E: Write access in WD_CMR is allowed. Other value: Write access in WD_CMR is prohibited. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary – – ...
Page 110
... WDOVF: Watchdog Overflow (Code Label WD_WDOVF watchdog overflow watchdog overflow has occurred since the last restart of the watchdog counter or since internal or external reset. AT91FR40162S Preliminary 110 – – – – – – ...
Page 111
... SF: Special Function Registers The AT91FR40162S provides registers to implement the following special functions. • Chip identification • RESET status • Protect Mode (see 16.1 Chip Identification Table 16-1 provides the Chip ID values for the products as listed. Table 16-1. Chip ID Values Product ...
Page 112
... Table 16-2. SF Memory Map Offset Register 0x00 Chip ID Register 0x04 Chip ID Extension Register 0x08 Reset Status Register 0x10 Reserved 0x14 Reserved 0x18 Protect Mode Register AT91FR40162S Preliminary 112 Name Access SF_CIDR Read-only SF_EXID Read-only SF_RSR Read-only – – – – SF_PMR Read/Write ...
Page 113
... NVPTYP Size 0 None 1 32K bytes 1 64K bytes 1 128K bytes 0 256K bytes Reserved Size 0 None Reserved AT91FR40162S Preliminary 26 25 ARCH 18 17 VDSIZ 10 9 NVPSIZ VERSION Code Label SF_NVPSIZ SF_NVPSIZ_NONE SF_NVPSIZ_32K SF_NVPSIZ_64K SF_NVPSIZ_128K SF_NVPSIZ_256K Code Label SF_NVDSIZ SF_NVDSIZ_NONE – – ...
Page 114
... NVPTYP: Non Volatile Program Memory Type NVPTYP • EXT: Extension Flag (Code Label SF_EXT Chip ID has a single register definition without extensions extended Chip ID exists (to be defined in the future). AT91FR40162S Preliminary 114 Size 0 None 1 1K bytes 0 2K bytes 0 4K bytes 0 8K bytes Reserved AT91x40yyy Type Reserved “ ...
Page 115
... RESET: Reset Status Information This field indicates whether the reset was demanded by the external system (via NRST the Watchdog internal reset request. Reset Cause of Reset 0x6C External Pin 0x53 Internal Watchdog 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary – – – – ...
Page 116
... Write access in SF_PMR is allowed. Other value: Write access in SF_PMR is prohibited. • AIC: AIC Protect Mode Enable (Code Label SF_AIC The Advanced Interrupt Controller runs in Normal Mode The Advanced Interrupt Controller runs in Protect Mode. See Section 13.10 ”Protect Mode”, on page AT91FR40162S Preliminary 116 PMRKEY 21 ...
Page 117
... USART: Universal Synchronous Asynchronous Receiver Transmitter The AT91FR40162S provides two identical, full-duplex, universal synchronous/asynchronous receiver/transmitters that interface to the APB and are connected to the Peripheral Data Controller. The main features are: • Programmable Baud Rate Generator • Parity, Framing and Overrun Error Detection • ...
Page 118
... After a hardware reset, the USART pins are not enabled by default (see must configure the PIO Controller before enabling the transmitter or receiver the user selects one of the internal clocks, SCK can be configured as a PIO. AT91FR40162S Preliminary 118 ”PIO: Parallel I/O Controller” on page 91). The user 6174B– ...
Page 119
... In all cases external clock is used, the duration of each of its levels must be longer than the system clock (MCK) period. The external clock frequency must be at least 2.5 times lower than the system clock. Selected Clock = Selected Clock = CLK 16-bit Counter OUT > SYNC USCLKS [1] AT91FR40162S Preliminary SYNC 0 Divide Baud Rate Clock 119 ...
Page 120
... When configured for synchronous operation (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate clock low level is detected considered as a start. Data bits, parity bit and stop bit are sampled and the receiver waits for the next start bit. See example in AT91FR40162S Preliminary 120 RXD True Start Detection 0 ...
Page 121
... TIMEOUT bit in US_CSR is set. The user can restart the wait for a first character with the STTTO (Start Time-out) bit in US_CR. Calculation of time-out duration: 6174B–ATARM–07-Nov-05 SCK RXD True Start Detection = Value x Duration AT91FR40162S Preliminary Parity Bit x 4 Bit period Stop Bit 121 ...
Page 122
... US_CR. In this case, the next byte written to US_THR will be transmitted as an address. After this any byte transmitted will have the parity bit cleared. Figure 17-6. Synchronous and Asynchronous Modes: Character Transmission Example: 8-bit, parity enabled 1 stop Baud Rate AT91FR40162S Preliminary 122 Idle state duration between two characters Clock ...
Page 123
... Send the STTBRK command (write 0x0200 to US_CR) 3. Wait for the transmitter ready (TXRDY = 1 in US_CSR) 4. Send the STPBRK command (write 0x0400 to US_CR) The next byte can then be sent: 5. Wait for the transmitter ready (TXRDY = 1 in US_CSR) 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary 123 ...
Page 124
... Asynchronous Mode or at least one sample in Synchronous Mode. RXBRK is also asserted when an end of break is detected. Both the beginning and the end of a break can be detected by interrupt if the bit US_IMR.RXBRK is set. AT91FR40162S Preliminary 124 6174B–ATARM–07-Nov-05 ...
Page 125
... Advanced Interrupt Controller. US_IMR (Interrupt Mask Register) indicates the status of the corresponding bits. When a bit is set in US_CSR and the same bit is set in US_IMR, the interrupt line is asserted. 6174B–ATARM–07-Nov-05 The PDC is disabled if 9-bit character length is selected (MODE9 = 1) in US_MR. AT91FR40162S Preliminary 125 ...
Page 126
... RXD pin level has no effect and the TXD pin is held high idle state. Remote Loopback Mode directly connects the RXD pin to the TXD pin. The Transmitter and the Receiver are disabled and have no effect. This mode allows bit by bit re-transmission. Figure 17-7. Channel Modes AT91FR40162S Preliminary 126 Automatic Echo Receiver ...
Page 127
... Receiver Time-out Register 0x28 Transmitter Time-guard Register 0x2C Reserved 0x30 Receive Pointer Register 0x34 Receive Counter Register 0x38 Transmit Pointer Register 0x3C Transmit Counter Register 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary Name Access US_CR Write-only US_MR Read/Write US_IER Write-only US_IDR Write-only US_IMR Read-only US_CSR ...
Page 128
... Resets the status bits PARE, FRAME, OVRE and RXBRK in the US_CSR. • STTBRK: Start Break (Code Label US_STTBRK effect break is not being transmitted, start transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. AT91FR40162S Preliminary 128 – ...
Page 129
... STTTO: Start Time-out (Code Label US_STTTO effect Start waiting for a character before clocking the time-out counter. • SENDA: Send Address (Code Label US_SENDA effect Multi-drop Mode only, the next character written to the US_THR is sent with the address bit set. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary 129 ...
Page 130
... X • CHRL: Character Length CHRL Start, stop and parity bits are added to the character length. • SYNC: Synchronous Mode Select (Code Label US_SYNC USART operates in Asynchronous Mode USART operates in Synchronous Mode. AT91FR40162S Preliminary 130 – – – – – – ...
Page 131
... CHRL defines character length 9-bit character length. • CKLO: Clock Output Select (Code Label US_CLKO The USART does not drive the SCK pin The USART drives the SCK pin if USCLKS[ 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary Synchronous (SYNC = 1) 1 stop bit Reserved 2 stop bits Reserved ...
Page 132
... OVRE: Enable Overrun Error Interrupt (Code Label US_OVRE effect Enables Overrun Error Interrupt. • FRAME: Enable Framing Error Interrupt (Code Label US_FRAME effect Enables Framing Error Interrupt. • PARE: Enable Parity Error Interrupt (Code Label US_PARE effect Enables Parity Error Interrupt. AT91FR40162S Preliminary 132 – – – 21 ...
Page 133
... TIMEOUT: Enable Time-out Interrupt (Code Label US_TIMEOUT effect Enables Reception Time-out Interrupt. • TXEMPTY: Enable TXEMPTY Interrupt (Code Label US_TXEMPTY effect Enables TXEMPTY Interrupt. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary 133 ...
Page 134
... OVRE: Disable Overrun Error Interrupt (Code Label US_OVRE effect Disables Overrun Error Interrupt. • FRAME: Disable Framing Error Interrupt (Code Label US_FRAME effect Disables Framing Error Interrupt. • PARE: Disable Parity Error Interrupt (Code Label US_PARE effect Disables Parity Error Interrupt. AT91FR40162S Preliminary 134 – – – 21 ...
Page 135
... TIMEOUT: Disable Time-out Interrupt (Code Label US_TIMEOUT effect Disables Receiver Time-out Interrupt. • TXEMPTY: Disable TXEMPTY Interrupt (Code Label US_TXEMPTY effect Disables TXEMPTY Interrupt. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary 135 ...
Page 136
... Overrun Error Interrupt is Enabled • FRAME: Mask Framing Error Interrupt (Code Label US_FRAME Framing Error Interrupt is Disabled 1 = Framing Error Interrupt is Enabled • PARE: Mask Parity Error Interrupt (Code Label US_PARE Parity Error Interrupt is Disabled 1 = Parity Error Interrupt is Enabled AT91FR40162S Preliminary 136 – – ...
Page 137
... TIMEOUT: Mask Time-out Interrupt (Code Label US_TIMEOUT Receive Time-out Interrupt is Disabled 1 = Receive Time-out Interrupt is Enabled • TXEMPTY: Mask TXEMPTY Interrupt (Code Label US_TXEMPTY TXEMPTY Interrupt is Disabled TXEMPTY Interrupt is Enabled. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary 137 ...
Page 138
... FRAME: Framing Error (Code Label US_FRAME stop bit has been detected low since the last “Reset Status Bits” command least one stop bit has been detected low since the last “Reset Status Bits” command. AT91FR40162S Preliminary 138 – ...
Page 139
... RXCHR: Received Character Last character received if RXRDY is set. When number of data bits is less than 8 bits, the bits are right-aligned. All non-significant bits read zero. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary – – – – – – 13 ...
Page 140
... TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. When number of data bits is less than 8 bits, the bits are right-aligned. AT91FR40162S Preliminary 140 – – – – – – ...
Page 141
... Baud Rate (Asynchronous Mode) = Selected Clock / ( 65535 Baud Rate (Synchronous Mode) = Selected Clock / CD Notes: 1. Clock divisor bypass ( must not be used when internal clock MCK is selected (USCLKS = 0 Synchronous Mode, the value programmed must be even to ensure a 50:50 mark:space ratio. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary – – – ...
Page 142
... When a value is written to this register, a Start Time-out Command is automatically performed Disables the RX Time-out function. The Time-out counter is loaded with TO when the Start Time-out Command is given or when each new data character 255 received (after reception has started). Time-out duration = Bit period AT91FR40162S Preliminary 142 – – – ...
Page 143
... USART Receive Pointer Register Name: US_RPR Access Type: Read/Write Reset Value: 0 Offset: 0x30 • RXPTR: Receive Pointer RXPTR must be loaded with the address of the receive buffer. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary – – – – – – – – – 5 ...
Page 144
... Start Peripheral Data transfer if RXRDY is active. 17.10.14 USART Transmit Pointer Register Name: US_TPR Access Type: Read/Write Reset Value: 0 Offset: 0x38 • TXPTR: Transmit Pointer TXPTR must be loaded with the address of the transmit buffer. AT91FR40162S Preliminary 144 – – – 21 4920 19 – – – RXCTR 5 4 ...
Page 145
... TXCTR: Transmit Counter TXCTR must be loaded with the size of the transmit buffer. 0: Stop Peripheral Data Transfer dedicated to the transmitter 65535: Start Peripheral Data transfer if TXRDY is active. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary – – – – – – ...
Page 146
... TC: Timer Counter The AT91FR40162S features a Timer Counter block which includes three identical 16-bit timer counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse gen- eration, delay timing and pulse width modulation. ...
Page 147
... MCK/32 TCLK1 TCLK2 MCK/128 MCK/1024 TCLK0 TCLK1 TIOA0 TIOA2 TCLK2 TCLK0 TCLK1 TCLK2 TIOA0 TIOA1 Timer Counter Block 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary XC0 Timer Counter TIOA Channel 0 XC1 TIOB XC2 TC0XC0S SYNC XC0 Timer Counter TIOA Channel 1 XC1 TIOB XC2 ...
Page 148
... Register) is set. The current value of the counter is accessible in real-time by reading TC_CV. The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. AT91FR40162S Preliminary 148 Description External Clock Inputs Capture Mode: General Purpose Input ...
Page 149
... In all cases external clock is used, the duration of each of its levels must be longer than the system clock (MCK) period. The external clock frequency must be at least 2.5 times lower than the system clock (MCK). CLKS MCK/2 MCK/8 MCK/32 MCK/128 MCK/1024 XC0 XC1 XC2 BURST 1 AT91FR40162S Preliminary CLKI Selected Clock 149 ...
Page 150
... TIOB is an output not selected to be the external trigger. 18.3.5 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes: AT91FR40162S Preliminary 150 Selected Trigger Clock CLKSTA ...
Page 151
... Whatever the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value may not read zero just after a trigger, espe- cially when a low frequency signal is selected as the clock. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary 151 ...
Page 152
... ETRGS: External Trigger Status An external trigger on TIOA or TIOB has been detected since the last read of the status Note: AT91FR40162S Preliminary 152 All the status bits are set when the corresponding event occurs and they are automatically cleared when the Status Register is read. ...
Page 153
... TIOA Timer Counter Channel 6174B–ATARM–07-Nov-05 CLKI 16-bit Counter SWTRG CLK OVF RESET Trig CPCTRG ETRGEDG Edge Detector LDRA Edge Detector loaded AT91FR40162S Preliminary CLKSTA CLKEN CLKDIS LDBSTOP LDBDIS Capture Capture Register A Register B LDRB Edge Detector INT Register C Compare RC = 153 ...
Page 154
... The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can be pro- grammed to set, clear or toggle the output as defined in the corresponding parameter in TC_CMR. AT91FR40162S Preliminary 154 6174B–ATARM–07-Nov-05 ...
Page 155
... TIOA Event Software Trigger External Event RC Compare RA Compare TIOB Event Software Trigger External Event RC Compare RB Compare All the status bits are set when the corresponding event occurs and they are automatically cleared when the Status Register is read. AT91FR40162S Preliminary 155 ...
Page 156
... Figure 18-5. Waveform Mode TCCLKS MCK/2 CLKI MCK/8 MCK/32 MCK/128 MCK/1024 XC0 XC1 XC2 BURST 1 SWTRG SYNC EEVT EEVTEDG Edge Detector TIOB Timer Counter Channel AT91FR40162S Preliminary 156 CLKSTA CLKEN Register A Register B Compare RA = Compare RB = 16-bit Counter CLK OVF RESET Trig CPCTRG ENETRG ...
Page 157
... Register C 0x20 Status Register 0x24 Interrupt Enable Register 0x28 Interrupt Disable Register 0x2C Interrupt Mask Register Note: 1. Read-only if WAVE = 0 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary Name Access See Table 18-3 See Table 18-3 See Table 18-3 TC_BCR Write-only TC_BMR Read/Write Name Access ...
Page 158
... Offset: 0xC0 31 30 – – – – – – – – • SYNC: Synchro Command effect Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. AT91FR40162S Preliminary 158 – – – – – – – – – 5 ...
Page 159
... TC0XC0S • TC1XC1S: External Clock Signal 1 Selection TC1XC1S • TC2XC2S: External Clock Signal 2 Selection TC2XC2S 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary – – – – – – – – – TC2XC2S Signal Connected to XC0 TCLK0 None TIOA1 TIOA2 Signal Connected to XC1 TCLK1 ...
Page 160
... Enables the clock if CLKDIS is not 1. • CLKDIS: Counter Clock Disable Command (Code Label TC_CLKDIS effect Disables the clock. • SWTRG: Software Trigger Command (Code Label TC_SWTRG effect software trigger is performed: the counter is reset and clock is started. AT91FR40162S Preliminary 160 – – ...
Page 161
... Selected BURST 0 0 The clock is not gated by an external signal 0 1 XC0 is ANDed with the selected clock 1 0 XC1 is ANDed with the selected clock 1 1 XC2 is ANDed with the selected clock 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary – – – – – – ...
Page 162
... LDRA: RA Loading Selection LDRA Edge 0 0 None 0 1 Rising edge of TIOA 1 0 Falling edge of TIOA 1 1 Each edge of TIOA AT91FR40162S Preliminary 162 Code Label TC_ETRGEDG TC_ETRGEDG_EDGE_NONE TC_ETRGEDG_RISING_EDGE TC_ETRGEDG_FALLING_EDGE TC_ETRGEDG_BOTH_EDGE Code Label TC_ABETRG TC_ABETRG_TIOB TC_ABETRG_TIOA Code Label TC_LDRA TC_LDRA_EDGE_NONE TC_LDRA_RISING_EDGE TC_LDRA_FALLING_EDGE TC_LDRA_BOTH_EDGE 6174B– ...
Page 163
... LDRB: RB Loading Selection LDRB Edge 0 0 None 0 1 Rising edge of TIOA 1 0 Falling edge of TIOA 1 1 Each edge of TIOA 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary Code Label TC_LDRB TC_LDRB_EDGE_NONE TC_LDRB_RISING_EDGE TC_LDRB_FALLING_EDGE TC_LDRB_BOTH_EDGE 163 ...
Page 164
... BURST: Burst Signal Selection BURST Selected BURST 0 0 The clock is not gated by an external signal XC0 is ANDed with the selected clock XC1 is ANDed with the selected clock XC2 is ANDed with the selected clock. AT91FR40162S Preliminary 164 BEEVT AEEVT – ENETRG ...
Page 165
... RC Compare resets the counter and starts the counter clock. • WAVE = 1 (Code Label TC_WAVE Waveform Mode is disabled (Capture Mode is enabled Waveform Mode is enabled. 6174B–ATARM–07-Nov-05 External Event TIOB Direction (1) Input Output Output Output AT91FR40162S Preliminary Code Label TC_EEVTEDG TC_EEVTEDG_EDGE_NONE TC_EEVTEDG_RISING_EDGE TC_EEVTEDG_FALLING_EDGE TC_EEVTEDG_BOTH_EDGE Code Label TC_EEVT TC_EEVT_TIOB TC_EEVT_XC0 TC_EEVT_XC1 ...
Page 166
... Toggle • ASWTRG: Software Trigger Effect on TIOA ASWTRG Effect 0 0 None 0 1 Set 1 0 Clear 1 1 Toggle AT91FR40162S Preliminary 166 Code Label TC_ACPA TC_ACPA_OUTPUT_NONE TC_ACPA_SET_OUTPUT TC_ACPA_CLEAR_OUTPUT TC_ACPA_TOGGLE_OUTPUT Code Label TC_ACPC TC_ACPC_OUTPUT_NONE TC_ACPC_SET_OUTPUT TC_ACPC_CLEAR_OUTPUT TC_ACPC_TOGGLE_OUTPUT Code Label TC_AEEVT TC_AEEVT_OUTPUT_NONE TC_AEEVT_SET_OUTPUT TC_AEEVT_CLEAR_OUTPUT ...
Page 167
... Toggle • BSWTRG: Software Trigger Effect on TIOB BSWTRG Effect 0 0 None 0 1 Set 1 0 Clear 1 1 Toggle 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary Code Label TC_BCPB TC_BCPB_OUTPUT_NONE TC_BCPB_SET_OUTPUT TC_BCPB_CLEAR_OUTPUT TC_BCPB_TOGGLE_OUTPUT Code Label TC_BCPC TC_BCPC_OUTPUT_NONE TC_BCPC_SET_OUTPUT TC_BCPC_CLEAR_OUTPUT TC_BCPC_TOGGLE_OUTPUT Code Label TC_BEEVT TC_BEEVT_OUTPUT_NONE TC_BEEVT_SET_OUTPUT ...
Page 168
... CV contains the counter value in real-time. 18.6.7 TC Register A Register Name: TC_RA Access Type: Read-only if WAVE = 0, Read/Write if WAVE = 1 Reset Value: 0 Offset: 0x14 31 30 – – – – • RA: Register A (Code Label TC_RA) RA contains the Register A value in real-time. AT91FR40162S Preliminary 168 – – – – – – – ...
Page 169
... RB contains the Register B value in real-time. 18.6.9 TC Register C Register Name: TC_RC Access Type: Read/Write Reset Value: 0 Offset: 0x1C 31 30 – – – – • RC: Register C (Code Label TC_RC) RC contains the Register C value in real-time. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary – – – – – – – – ...
Page 170
... RB Load has occurred since the last read of the Status Register, if WAVE = 0. • ETRGS: External Trigger Status (Code Label TC_ETRGS External trigger has not occurred since the last read of the Status Register External trigger has occurred since the last read of the Status Register. AT91FR40162S Preliminary 170 – ...
Page 171
... MTIOB: TIOB Mirror (Code Label TC_MTIOB TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary 171 ...
Page 172
... LDRAS: RA Loading (Code Label TC_LDRAS effect Enables the RA Load Interrupt. • LDRBS: RB Loading (Code Label TC_LDRBS effect Enables the RB Load Interrupt. • ETRGS: External Trigger (Code Label TC_ETRGS effect Enables the External Trigger Interrupt. AT91FR40162S Preliminary 172 – – – 21 ...
Page 173
... ETRGS: External Trigger (Code Label TC_ETRGS effect Disables the External Trigger Interrupt. 6174B–ATARM–07-Nov- – – – – – – – – – LDRAS CPCS CPBS AT91FR40162S Preliminary 26 25 – – – – – – CPAS LOVRS 24 – 16 – 8 – 0 COVFS 173 ...
Page 174
... The Load RA Interrupt is enabled. • LDRBS: RB Loading (Code Label TC_LDRBS The Load RB Interrupt is disabled The Load RB Interrupt is enabled. • ETRGS: External Trigger (Code Label TC_ETRGS The External Trigger Interrupt is disabled The External Trigger Interrupt is enabled. AT91FR40162S Preliminary 174 – – – ...
Page 175
... AT91FR40162S Electrical Characteristics 19.1 Absolute Maximum Ratings Table 19-1. Absolute Maximum Ratings* Operating Temperature (Industrial Storage Temperature...................... - 150 C Voltage on Any Input Pin with Respect to Ground ..................................................-0.3V to max of V .......................................................... + 0.3V and 3.6V Maximum Operating Voltage (V DDIO Maximum Operating Voltage (V DDCORE Voltage with Respect to Ground......................-0.6V to +13.0V 6174B– ...
Page 176
... Input Capacitance IN I Static Current SC Notes Output Current at low level Pin Group 1 = NUB/NWR1, NWE/NWR0, NOE/NRD1 3. Pin Group 2 = D0-D15, A0/NLB, A1-A19, P28/A20/CS7, P29/A21/CS6, P30/A22/CS5, P31/A23/CS4, NCS0, NCS1, P26/NCS2, P27/NCS3 4. Pin Group 3 = All Others AT91FR40162S Preliminary 176 Conditions (2) (1) Pin Group (3) (1) Pin Group ...
Page 177
... V (max) = 0.4V. ILPP 6174B–ATARM–07-Nov-05 Condition I 0. MHz OUT mA RESET ( (max) = 3.6V. AT91FR40162S Preliminary Min Typ (3) Ai IHPP (4) ILPP A19 = A19 = Max Units 2 µA 10 µA 25 µ µA 0 I/O D OUT D IN High-Z High-Z High-Z Manufacturer (2) Code (2) Device Code 177 ...
Page 178
... Reset Normal Idle Note: Table 19-6. Peripheral PIO Controller Timer/Counter Channel Timer/Counter Block (3 Channels) USART AT91FR40162S Preliminary 178 = 1.8V the AT91EB40A Evaluation Board and are given DDCORE A Power Consumption on VDDCORE Conditions Fetch in ARM mode from internal SRAM All peripheral clocks activated ...
Page 179
... Conditions Conditions MCKO C derating MCKO MCKO C derating MCKO t CH 2.0V 0. 0.5 V 0.5 V DDIO DDIO t CDHL AT91FR40162S Preliminary Min Max 82.1 12.2 5.0 5.5 Min Max 4.4 6.6 0.199 0.295 4.5 6.7 0.153 0.228 0.8V 0. Min Max 3(t /2) 7(t CP ...
Page 180
... Figure 19-2. MCKO Relative to NRST NRST MCKO AT91FR40162S Preliminary 180 t D 6174B–ATARM–07-Nov-05 ...
Page 181
... I/O Power Supply given in is the capacitance load on the considered output pin. is the load derating factor depending on the capacitance load on the related output 1. The user must take into account the package capacitance load contribution (C Table 19-2 on page 176. AT91FR40162S Preliminary DDIO C + VDDIO SIGNAL ...
Page 182
... Temperature Derating Factor Figure 20-1. Derating Curve for Different Operating Temperatures 20.1.3 Core Voltage Derating Factor Figure 20-2. Core Voltage Derating Factor AT91FR40162S Preliminary 182 1.2 1.1 1 0.9 0.8 -60 -40 - Operating Temperature °C 3 2.5 2 1.5 1 0.5 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7 1.75 1.8 1.85 1.9 1.95 ...
Page 183
... IO Voltage Derating Factor Figure 20-3. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary Derating Factor for Different V DDIO 1,6 1,5 1,4 1,3 1,2 1,1 1 0,9 0,8 2 2,2 2,4 2,6 V DDIO Power Supply Levels Derating Factor for Typ Case is 1 2,8 3 3,2 3,4 Voltage Level ...
Page 184
... Waveform Total-count Detection mode. The inputs have to meet the minimum pulse width and minimum input period shown in Table 20-3. Symbol TC 1 Table 20-4. Symbol TC 2 AT91FR40162S Preliminary 184 20-2, and represented in Figure 20-4. USART Input Minimum Pulse Width Parameter SCK/RXD Minimum Pulse Width USART Minimum Input Period Parameter ...
Page 185
... Reset Minimum Pulse Width Parameter NRST Minimum Pulse Width RST and represented in Figure AIC Input Minimum Pulse Width Parameter FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Minimum Pulse Width AIC Input Minimum Period Parameter AIC Minimum Input Period AT91FR40162S Preliminary TC 2 3(t /2) CP Table 20-5 and as represented in Min Pulse-width 10 20-7 ...
Page 186
... ICE 2 ICE 3 ICE 4 ICE 5 ICE 6 ICE 7 ICE 8 ICE 9 AT91FR40162S Preliminary 186 MCKI AIC 1 PIO Input Minimum Pulse Width Parameter PIO Input Minimum Pulse Width PIO ICE Interface Timing Specifications Parameter Conditions NTRST Minimum Pulse Width NTRST High Recovery to TCK High NTRST High Removal from ...
Page 187
... Figure 20-9. ICE Interface Signal NTRST TMS/TDI 6174B–ATARM–07-Nov-05 ICE 0 TCK ICE 3 TDO ICE 8 ICE 9 AT91FR40162S Preliminary ICE ICE 2 1 ICE 5 ICE 4 ICE ICE 6 7 187 ...
Page 188
... MCKI Rising to NWR Inactive (Wait States) 10 EBI MCKI Rising D15 Out Valid 11 EBI NWR High to NUB Change 12 EBI NWR High to NLB/A0 Change 13 EBI NWR High A23 Change 14 EBI NWR High to Chip Select Inactive 15 AT91FR40162S Preliminary 188 Conditions NUB C derating NUB NLB C derating NLB ...
Page 189
... D0 - D15 In Hold after MCKI Falling Edge 26 EBI NRD High to NUB Change 27 EBI NRD High to NLB/A0 Change 28 EBI NRD High A23 Change 29 EBI NRD High to Chip Select Inactive 30 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary Conditions (1) C derating DATA C derating NWR (1) C derating DATA ...
Page 190
... If this condition is not met, the action depends on the read protocol intended for use. • Early Read Protocol: Programing an additional t • Standard Read Protocol: Programming an additional t 2. Applicable only for chip select programmed with 0 wait state. If this condition is not met, at least one wait state must be programmed. AT91FR40162S Preliminary 190 Conditions ...
Page 191
... EBI 33 EBI EBI 22 24 EBI 34 EBI 31 EBI 25 EBI EBI 9 7 EBI 19 EBI 8 EBI 11 EBI 16 1. Early Read Protocol. 2. Standard Read Protocol. AT91FR40162S Preliminary EBI 4 EBI 27-30 EBI 32 EBI 26 EBI 12-15 EBI 10 EBI 20 EBI EBI bis 17 18 EBI 18 No Wait Wait 191 ...
Page 192
... OE (3)( 20.4.1 AC Read Waveforms Figure 20-11. AC Read Waveforms RESET Notes: AT91FR40162S Preliminary 192 Parameter Read Cycle Time Address to Output Delay CE to Output Delay OE to Output Delay Output Float Output Hold from OE Address, whichever occurred first RESET to Output Delay (1) (2) (3) (4) ADDRESS ...
Page 193
... Figure 20-12. Input Test Waveforms and Measurement Level 20.4.3 Output Test Load Figure 20-13. Output Test Load 20.4.4 Pin Capacitance Table 20-15. Pin Capacitance MHz 25°C Symbol OUT Note: 1. This parameter is characterized and is not 100% tested. 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary < (1) Conditions OUT Typ ...
Page 194
... AH t Chip Select Setup Time CS t Chip Select Hold Time CH t Write Pulse Width ( Data Setup Time Data, OE Hold Time DH OEH t Write Pulse Width High WPH 20.5.1 WE Controlled Figure 20-14. WE Controlled AT91FR40162S Preliminary 194 Min Max Units 6174B–ATARM–07-Nov-05 ...
Page 195
... CE Controlled Figure 20-15. CE Controlled 6174B–ATARM–07-Nov-05 AT91FR40162S Preliminary 195 ...
Page 196
... Sector Erase Cycle Time (4K Word Sectors) SEC1 t Sector Erase Cycle Time (32K Word Sectors) SEC2 t Erase Suspend Time ES t Program Suspend Time PS 20.6.1 Program Cycle Waveforms Figure 20-16. Program Cycle Waveforms A19 DATA AT91FR40162S Preliminary 196 PROGRAM CYCLE WPH 555 AAA 555 ...
Page 197
... For chip erase, the address should be 555. For sector erase, the address depends on what sector erased. (See footnote page 61.) 3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H. AT91FR40162S Preliminary t WPH 555 555 AAA ...
Page 198
... Write Recovery Time WR Notes: 1. These parameters are characterized and not 100% tested. 2. See t spec in ”AC Flash Read Characteristics” on page OE 20.7.1 Data Polling Waveforms Figure 20-18. Data Polling Waveforms I/O7 A0-A19 AT91FR40162S Preliminary 198 (1) 192. t OEH HIGH Min Typ Max 10 10 ...
Page 199
... Toggling either both OE and CE will operate toggle bit. The t must be met by the toggling input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. AT91FR40162S Preliminary Min Typ Max 10 10 ...
Page 200
... From the first equation, the user can derive the estimated lifetime of the chip and thereby decide if a cooling device is necessary or not cooling device fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature T AT91FR40162S Preliminary 200 in °C can be obtained from the following: ...