SX28AC/SS Parallax Inc, SX28AC/SS Datasheet
SX28AC/SS
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SX28AC/SS Summary of contents
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... The deterministic architecture of the SX provides reliable performance for time-critical applications. In addition, Parallax and the Parallax logo are trademarks of Parallax, Inc trademark of Ubicom Inc, used with permission. © Parallax Inc. the SX architecture is flash-based and therefore reprogrammable. On-chip functions include a general- purpose 8-bit timer with prescaler, an analog comparator, ...
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... DC Characteristics................................................................... 41 17.3. AC Characteristics ................................................................... 42 17.4. Comparator DC and AC Specifications.................................... 42 17.5. Typical Performance Characteristics (25°C) ............................ 43 18.0 Package Dimensions..................................................46 18.1. SX20AC/SS ............................................................................. 46 18.2. SX28AC/SS ............................................................................. 47 18.3. SX28AC/DP............................................................................. 48 19.0 Manufacturing Information ........................................49 19.1. Reflow Peak Temperature ....................................................... 49 19.2. MSL3 Compliance ................................................................... 49 19.3. Green/RoHS Compliance ........................................................ 49 19.4. Stress Testing Data Summary ................................................. 49 Page www ...
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... Analog comparator support on Port B (RB0 OUT, RB1 IN-, RB2 IN+) • Selectable I/O operation synchronous to the oscillator clock © Parallax Inc. Hardware Peripheral Features • One 8-bit Real Time Clock/Counter (RTCC) with programmable 8-bit prescaler • Watchdog Timer (shares the RTCC prescaler) • ...
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... Program structure commands including BRANCH, DO..LOOP, GOTO, GOSUB, IF..THEN..ELSE • Numeric formatters • WORD variable support • Frequency generation with FREQOUT © Parallax Inc. • Synchronous serial communication for I SPI • Asynchronous serial communication with SERIN and SEROUT • Table data storage and retrieval with LOOKUP, LOOKDOWN • ...
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... Parallax SX20AC/SX28AC 1.8. Part Numbering Device Part# Pins I/O SX20AC/ SX20AC/SS-G SX28AC/ SX28AC/DP-G SX28AC/ SX28AC/SS-G * Ratings are preliminary © Parallax Inc. Table 1-1: Part Numbering EE/Flash RAM Voltage (Words) (Bytes) Range (V) 3.0 – 5.5 2K 137 3.0 – 5.5 2K 136 3.0 – 5.5 ...
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... V ss Note input output, I/O = Input/Output Power, TTL = TTL input, CMOS = CMOS input Schmitt Trigger input, MIWU = Multi-Input Wakeup input. © Parallax Inc. Figure 2-1: Pin Assignments Table 2-1: Pin Descriptions Description Bidirectional I/O Pin; symmetrical source / sink capability Bidirectional I/O Pin; symmetrical source / sink capability Bidirectional I/O Pin ...
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... Parallax SX20AC/SX28AC 2.3. Typical Connection Diagrams Note: The 10 kΩ resistor connected to the MCLR pin is not needed when controlled externally. Note: The 10 kΩ resistor connected to the MCLR pin is not needed when controlled externally. © Parallax Inc. Page www.parallax.com Rev 1.6 11/20/2006 ...
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... Parallax SX20AC/SX28AC Typical Connection Diagrams (continued) Note: The 10 kΩ resistor connected to the MCLR pin is not needed when controlled externally. © Parallax Inc. Page www.parallax.com Rev 1.6 11/20/2006 ...
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... RA, RB, and RC file registers at data memory addresses 05h, 06h, and 07h, respectively. Writing to a port data register sets the voltage levels of the © Parallax Inc. registers associated with Port A are not used. The least significant bit of the registers corresponds to the least significant port pin ...
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... Port B and Port C are both eight bits wide, so the full widths of the RB and RC registers are used. © Parallax Inc. When a write is performed to a bit position for a port that has been configured as an input, a write to the port data register is still performed, but it has no immediate effect on the pin ...
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... W,M (move MODE register to W) The value contained in the MODE register determines which port control register is accessed by the © Parallax Inc. “mov !rx,W” instruction as indicated in Table 2-1. MODE register values not listed in the table are reserved for future expansion and should not be used. Therefore, the MODE register should always contain a value from 08h to 0Fh ...
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... Each register bit selects the edge sensitivity of the Port B input pin for MIWU operation. Clear the bit sense rising (low-to-high) edges. Set the bit sense falling (high-to-low) edges. © Parallax Inc. WKPND_B: Wakeup Pending Bit Register (MODE=09h) When you access the WKPND_B register using “ ...
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... STATUS register is accessible during run time, except that bits PD and TO are read-only recommended that only SETB and CLRB instructions be used on this © Parallax Inc. register. Care should be exercised when writing to the STATUS register as the ALU status bits are updated upon completion of the write operation, possibly leaving the STATUS register with a result that is different than intended ...
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... RTCC roll-over interrupt is enabled 1 = RTCC roll-over interrupt is disabled RTCC increment select: RTS 0= RTCC increments on internal instruction cycle 1 = RTCC increments upon transition on RTCC pin © Parallax Inc. RTE_ES RTCC edge select: PS2 PS1 PS0 Bit 0 PSA PS2-PS0 : Prescaler divider (see table below) PS2, PS1, PS0 Upon reset, all bits in the OPTION register are set to 1 ...
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... HS3 - high speed crystal/resonator/external crystal oscillator (1 MHz to 75 MHz) 111b = RC network - OSC2 is pulled high with a weak pullup (no CLKOUT output) Note: The frequencies are target values. © Parallax Inc. fly” during normal device operation. Instead, the FUSE and FUSEX registers can only be accessed when the SX device is being programmed ...
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... LOW 11b = HIGH 10b = maximum threshold voltage BP1:BPO 00b = 1 page, 1 bank 01b = 2 pages, 1 bank 10b = 4 pages, 4 banks 11b = 4 pages, 8 banks 5.3. DEVICE Word (Hard-Wired Read-Only Bit 11 © Parallax Inc. OPTIONX / BOR1 BOR0 CF STACKX (default configuration Page www.parallax.com BORTR1 BORTR0 ...
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... The stack is physically and logically separate from data RAM. The program cannot read or write the stack. © Parallax Inc. 6.2. Data Memory The data memory consists of 136 bytes of RAM, organized as eight banks of 16 registers plus eight registers which are not banked ...
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... Parallax SX20AC/SX28AC © Parallax Inc. Figure 6-1: Data Memory Organization Page www.parallax.com Rev 1.6 11/20/2006 ...
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... Port B is used to support this feature. Figure 7-1: Multi-Input Wakeup Block Diagram © Parallax Inc. The WKEN_B register (Wakeup Enable Regis ter) allows any Port B pin or combination of pins to cause the wakeup. Clearing a bit in the WKEN_B register enables the wakeup on the corresponding Port B pin ...
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... Port B accesses. Otherwise, the “mov” instruction does not perform an exchange, but only moves data from the source to the destination. © Parallax Inc. Here is an example of a program segment that configures the RB0, RB1, and RB2 pins to operate as Multi Input Wakeup/Interrupt pins, sensitive to falling edges: ...
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... Port individually enabled or disabled. Clearing a bit in the WKEN_B register enables the interrupt on the corresponding Port B pin. The WKED_B selects the © Parallax Inc. transition edge to be either positive or negative. The WKEN_B and WKED_B registers are set to FFh upon reset. Setting a bit in the WKED_B register selects the falling edge while clearing the bit selects the rising edge on the corresponding Port B pin ...
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... Note: the interrupt logic has its own single-level stack and is not part of the CALL subroutine stack. © Parallax Inc external interrupt occurs during the interrupt routine, the pending register will be updated but the trigger will be ignored unless interrupts are disabled at the beginning of the interrupt routine and enabled again at the end ...
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... OSC2/CLKOUT pin should be left open. Table 9-1: External Component Selection for Crystal Oscillator (V FOSC2:FOSC0 Crystal Frequency 010 4 MHz 011 8 MHz 011 20 MHz 011 32 MHz 100 50* MHz * 50 MHz fundamental crystal © Parallax Inc. OSC1/CLKIN and to the circuit 9-2 shows the Page www ...
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... CSACV33.00MXJ040 100 33 MHz CSTCV33.00MXJ040 101 50 MHz CSA50.00MXZ040 101 50 MHz CST50.00MXW0H3 101 50 MHz CSACV50.00MXJ040 101 50 MHz CSTCV50.00MXJ0H3 Table 9-3: Clock Devices Available through Parallax Inc. Parallax Stock# Frequency 250-04050 4 MHz 250-14050 4 MHz 250-02060 20 Mhz 250-12060 20 MHz 250-05060 50 MHz 250-15060 50 MHz 252-00005 75 MHz © ...
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... In addition, the oscillator frequency will vary from unit to unit due to normal manufacturing process variations. Furthermore, the difference in lead © Parallax Inc. frame capacitance between package types also affects the oscillation frequency, especially for low C values. The external R and C component tolerances contribute to oscillator frequency variation as well ...
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... Setting the control bit selects the falling edge to increment the counter. Clearing the bit selects the rising edge. © Parallax Inc. The RTCC generates an interrupt as a result of an RTCC rollover from 0FF to 000. There is no interrupt pending bit to indicate the overflow occurrence. The RTCC register must be sampled by the program to determine any overflow occurrence ...
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... Z bit in STATUS reg ;(0 => RB2<RB1) jmp rb2_hi ;jump only if RB2>RB1 © Parallax Inc. The final “mov” instruction in this example performs an exchange of data between the working register (W) and the CMP_B register. This exchange occurs only with Port B accesses. Otherwise, the “mov” instruction does not perform an exchange, but only moves data from the source to the destination ...
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... Figure 12-1 shows a power-up sequence where MCLR is not tied to the V pin and V signal is allowed to rise DD DD © Parallax Inc. and stabilize before MCLR pin is brought high. The device will actually come out of reset T MCLR goes high. The brown-out circuitry resets the chip when device power (V ...
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... Figure 12-3: Time-Out Sequence on Power-Up ( MCLR not tied to Vdd): Fast Vdd Rise Time Figure 12-4: Time-Out Sequence on Power-Up ( MCLR not tied to Vdd): Slow Vdd Rise Time © Parallax Inc. via a 10K resistor. DD signal is stable DD Figure 12-5: External Power-On Reset Circuit ...
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... Note 2: External reset during © Parallax Inc. an unknown value should be initialized by the software to a known value; you cannot simply test the initial state and rely on it starting in that state consistently. Table 14-1 lists the SX registers and shows the state of each register upon different reset ...
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... On the fourth clock cycle, the first instruction’s results are © Parallax Inc. written to its destination, the second instruction is executed, the third instruction is decoded, and the fourth instruction is fetched. Once the pipeline is full, instructions are executed at the rate of one per clock cycle ...
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... The instruction set contains instructions to set, reset, and test individual bits in data memory. The device is capable of bit addressing anywhere in data memory. © Parallax Inc. 15.7. The device contains three registers associated with each I/O port. The first register (Data Direction Register), configures each port pin as a Hi-Z input or output ...
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... Counter. This means that the call destination must start in the lower half of any page. For example, 00h-0FFh, 200h2FFh, 400h-4FFh, etc. © Parallax Inc. 15.10.4. Page Call Operation When a subroutine that resides on a different page is called, the page select bits must contain the proper values to point to the desired page before the call instruction is executed ...
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... File register address bit in opcode k Constant value bit in opcode © Parallax Inc. SB bit (bit test file register and skip if bit set). These instructions will cause the next instruction to be skipped if the tested condition is true skip instruction is immediately followed by a PAGE or BANK instruction (and the tested condition is true) then two instructions are skipped and the operation consumes three cycles ...
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... XOR W,fr XOR of W and fr into fr) XOR W,#lit XOR of W and Literal into lit) © Parallax Inc. In some cases, the exact number of cycles depends on the outcome of the instruction (such as the test-and-skip instructions) or the clocking mode (Slow or Turbo). In those cases, all possible numbers of cycles are shown in the table ...
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... Test Bit in fr and Skip if set (test fr.bit and skip SB fr.bit next instruction if bit is 1) SETB fr.bit Set Bit in fr (fr.bit = 1) Test Bit in fr and Skip if clear ( test fr.bit and skip SNB fr.bit next instruction if bit is 0) © Parallax Inc. SX Instruction Set: Arithmetic and Shift Operations Clock Cycles (Slow Mode ...
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... Move W to Port Rx control register: rx <=> W (exchange W and WKPND_B or CMP_B MOV !rx,W w (move for all other port control registers) MOV !OPTION,W Move W to OPTION register (OPTION = W) TEST fr Test fr for zero ( set or clear Z bit) © Parallax Inc. SX Instruction Set: Data Movement Instructions Native Clock Cycles (Slow Mode ...
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... FSR(7:5) = addr8(7:5) Read word from Instruction memory IREAD MODE:W = data at (MODE:W) Load Page number into STATUS(7:5) PAGE addr12 STATUS(7:5) = addr12(11:9) Power down mode SLEEP WDT = 00h stop oscillator ( clears prescaler if assigned) © Parallax Inc. Clock Cycles Clock Cycles (Slow Mode) (Turbo ...
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... Note 3: The assembler converts the SKIP instruction into a SNB or SB instruction that tests the least significant bit of the program counter, choosing SNB that the tested condition is always true. The instruction takes 4 cycles in the Slow clocking mode or 2 cycles in theTurbo clocking mode. © Parallax Inc. instruction carry), which is interpreted the same as the instruction “ ...
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... Max. current into V pin dd Max. DC current into an input pin with internal protection diode forward biased Max. allowable sink current per I/O pin Max allowable source current per I/O pin © Parallax Inc. Table 17-1: Absolute Maximum Ratings Page www.parallax.com -40 ° +85 ° C -65 ° ...
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... TTL Logic High Logic Low Input Leakage Current I il Weak Pullup Current I ip Output High Voltage Ports Port A Output Low Voltage V ol All Ports © Parallax Inc. Conditions MHz osc MHz osc MHz osc MHz (External OSC) dd osc MHz (Crystal) ...
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... Note: Data in the Typical (“TYP”) column °C unless otherwise stated. 17.4. Comparator DC and AC Specifications (50 MHz and 75 MHz Operation) Parameter Input Offset Voltage Input Common Mode Voltage Range Voltage Gain DC Supply Current (enabled) Response Time © Parallax Inc. Min Typ Max Units 1.0 4.0 ...
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... Parallax SX20AC/SX28AC 17.5. Typical Performance Characteristics (25°C) © Parallax Inc. Page www.parallax.com Rev 1.6 11/20/2006 ...
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... Parallax SX20AC/SX28AC 17.5. Typical Performance Characteristics (25°C) Continued © Parallax Inc. Page www.parallax.com Rev 1.6 11/20/2006 ...
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... Parallax SX20AC/SX28AC 17.5. Typical Performance Characteristics (25°C) Continued © Parallax Inc. Page www.parallax.com Rev 1.6 11/20/2006 ...
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... Parallax SX20AC/SX28AC 18.0 PACKAGE DIMENSIONS 18.1. SX20AC/SS © Parallax Inc. Page www.parallax.com Rev 1.6 11/20/2006 ...
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... Parallax SX20AC/SX28AC 18.2. SX28AC/SS © Parallax Inc. Page www.parallax.com Rev 1.6 11/20/2006 ...
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... Parallax SX20AC/SX28AC 18.3. SX28AC/DP © Parallax Inc. Page www.parallax.com Rev 1.6 11/20/2006 ...
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... Parallax Research and Development team, contact Parallax Sales or Tech Support. Sales/Tech Support: (916) 624-8333 Toll Free in the US: 1-888-512-1024 Sales: sales@parallax.com Tech Support: support@parallax.com Page www.parallax.com unbiased HAST Stock Code Tested SX20AC/SS-G 20 SX28AC/SS-G 20 SX28AC/DP-G 17 SX48BD-G 20 Subtotal 77 SX20AC/SS-G 20 SX28AC/SS-G 20 SX28AC/DP-G 17 SX48BD-G 20 Subtotal 77 Rev 1.6 11/20/2006 192 hours, Passed ...
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... Parallax SX20AC/SX28AC © Parallax Inc. Page www.parallax.com Rev 1.6 11/20/2006 ...
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... Parallax SX20AC/SX28AC © Parallax Inc. Page www.parallax.com Rev 1.6 11/20/2006 ...