CY8C26443-24PVXI Cypress Semiconductor Corp, CY8C26443-24PVXI Datasheet - Page 39

• Manufacturer Part Number: CY8C26443-24PVXI
• Description: IC MCU 16K FLASH 256B 28-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ CY8C26xxxr

Specifications of CY8C26443-24PVXI

• Core Processor: M8C
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.25 V
• Data Converters: A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Technology: CMOS
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Package Type: SSOP
• Screening Level: Industrial
• Pin Count: 28
• Mounting: Surface Mount
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 428-1643

The following diagram shows the PSoC MCU Clock Tree of signals 48M through SLP:
7.2.1
The CPU is clocked off the CPU system-clocking signal,
which can be configured to run at one of eight rates. This
selection is independent from all other clock selection
functions. It is completely safe for the CPU to change its
clock rate without a timing hazard. The CPU clock period
is determined by setting the CPU[2:0] bits in the Oscilla-
tor Control 0 Register (OSC_CR0).
September 5, 2002
PLL Lock Enable
Vcc
Vcc
OSC_CR0[6]
CPU and Sleep Timer Clock Options
Lock Loop
Phase
P1[0]
P1[1]
ILO Trim Register
ECO Trim Register
Figure 9: PSoC MCU Clock Tree of Signals
Low Speed
IMO Trim Register
Oscillator
ECO_TR[7:0]
Oscillator
ILO_TR[7:0]
Oscillator
IMO_TR[7:0]
External
Internal
Crystal
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
Internal
÷ 732
Main
48 MHz
24 MHz
The sleep timer is clocked off the SLP system-clocking
signal. The SLEEP[1] and SLEEP[0] bits in the Oscillator
Control 0 Register (OSC_CR0) allow the user to select
from the four available periods.
32 kHz Select
OSC_CR0[7]
Sleep Clock Div isor
24V1 Clock Div isor
24V2 Clock Div isor
CPU Clock Div isor
OSC_CR0[4:3]
OSC_CR1[7:4]
OSC_CR1[3:0]
OSC_CR0[2:0]
÷ 1
÷ 2
÷ 4
÷ 8
÷ 16
÷ 32
÷ 128
÷ 256
÷ 2
÷ 2
÷ 2
÷ 2
÷ n
÷ n
6
9
1 2
1 5
48M
24M
24V2
24V1
CPU
SLP
32K
Clocking
39