W90N740CDG Nuvoton Technology Corporation of America, W90N740CDG Datasheet - Page 65

• Manufacturer Part Number: W90N740CDG
• Description: IC MCU ARM7 TDMI 176-LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W90r

Specifications of W90N740CDG

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, Ethernet, UART/USART, USB
• Peripherals: DMA, POR, WDT
• Number Of I /o: 21
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

DCAEN [1] ： D-Cache enable
When set to “1”, Data cache operation is enabled.
D-Cache is disabled after reset.
ICAEN [0] ： I-Cache enable
When set to “1”, Instruction cache operation is enabled.
I-Cache is disabled after reset.
Cache Control Register (CAHCON)
Cache controller supports one Control register used to control the following operations.
These command set bits in CAHCON register are auto-clear bits. As the end of execution, that command
set bit will be cleared to “0” automatically.
DRWB [7] ：Drain write buffer
Forces write buffer data to be written to main memory.
ULKS [6] ：Unlock I-Cache/D-Cache single line
Unlocks the I-Cache/D-Cache per line. Both WAY and ADDR bits in CAHADR register must be
specified.
ULKA [5] ：Unlock I-Cache/D-Cache entirely
Unlocks the entire I-Cache/D-Cache, the lock bit “L” will be cleared to 0.
REGISTER
CAHCON
DRWB
Flush I-Cache and D-Cache
Load and lock I-Cache and D-Cache
Unlock I-Cache and D-Cache
Drain write buffer
31
23
15
7
0xFFF0.2004
ULKS
ADDRESS
30
22
14
6
ULKA
29
21
13
5
R/W Cache control register
R/W
LDLK
28
20
12
4
RESERVED
RESERVED
RESERVED
- 62 -
W90N740CD/W90N740CDG
FLHS
DESCRIPTION
27
19
11
3
FLHA
26
18
10
2
DCAH
25
17
9
1
RESET VALUE
0x0000.0000
ICAH
24
16
8
0