STR750FV2H6 STMicroelectronics, STR750FV2H6 Datasheet - Page 63

• Manufacturer Part Number: STR750FV2H6
• Description: MCU 32BIT 256KB FLASH 100-LFBGA
• Manufacturer: STMicroelectronics
• Series: STR7r

Specifications of STR750FV2H6

• Core Processor: ARM7
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, SPI, SSI, SSP, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFBGA
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: CAN, I2C, SPI, SSI, SSP, USB
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 72
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: MCBSTR750UME - BOARD EVAL MCBSTR750 + ULINK-MEMCBSTR750U - BOARD EVAL MCBSTR750 + ULINK2497-5988 - BOARD DEVELOPMENT LOVE STR750497-5754 - KIT STARTER IAR STR750497-5753 - KIT STARTER KEIL FOR STR7/STR9497-5752 - KIT STARTER IAR FOR STR7/STR9497-5751 - KIT STARTER HITEX FOR STR750497-5748 - BOARD EVALUATION FOR STR750XF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5649

STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Figure 28. SPI configuration - master mode, single transfer
Figure 29. SPI configuration - master mode, continuous transfer, CPHA=0
Figure 30. SPI configuration - master mode, continuous transfer, CPHA=1
MISO
MOSI
MOSI
MISO
MOSI
MISO
NSS
NSS
NSS
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
INPUT
OUTPUT
CPOL=0
CPOL=0
CPOL=1
CPOL=1
OUTPUT
OUTPUT
OUTPUT
INPUT
OUTPUT
OUTPUT
INPUT
DONT CARE
DONT CARE
1 OR 0
DONT CARE
t
NSSLQV
1 OR 0
1 OR 0
edge
trigger
t
NSSLQV
trigger
t
SCKQV
MSB OUT
MSB IN
t
su(MISO)
sample
MSB OUT
MSB IN
sample
sample
sample
edge
edge
trigger
MSB IN
trigger
MSB OUT
t
sample trigger
h(MISO)
sample
trigger
FRAME 1
edge
trigger
edge
trigger sample
t
FRAME 1
c(SCK)
t
sample trigger
SCKQX
t
t
t
w(SCKH)
w(SCKL)
c(SCK)
trigger sample
BIT OUT
samlpe trigger
BIT IN
t
c(SCK)
trigger sample
LSB OUT
LSB IN
LSB OUT
LSB IN
sample
trigger
trigger
MSB OUT
MSB IN
sample
DONT CARE
sample
1.5*t
sample
edge
FRAME 2
edge
t
t
r(SCK)
f(SCK)
c(SCK)
Electrical parameters
trigger
LSB OUT
t
NSSLQV
LSB IN
sample trigger
trigger
t
SCKNSSH (CPHA=1)
MSB OUT
MSB IN
edge
sample
t
SCKNSSH (CPHA=0)
FRAME 2
t
SCKQX
trigger
sample trigger
1 OR 0
sample
DONT
CARE
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