AD604ARZ Analog Devices Inc, AD604ARZ Datasheet - Page 20

• Manufacturer Part Number: AD604ARZ
• Description: IC AMP VGA DUAL ULN 40MA 24SOIC
• Manufacturer: Analog Devices Inc
• Series: X-AMP®r
• Type: Var Gain Ampr

Specifications of AD604ARZ

• Amplifier Type: Variable Gain
• Number Of Circuits: 2
• Slew Rate: 170 V/µs
• -3db Bandwidth: 40MHz
• Current - Input Bias: 400nA
• Current - Supply: 32mA
• Current - Output / Channel: 40mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• No. Of Amplifiers: 2
• Bandwidth: 40MHz
• Gain Accuracy: 3dB
• No. Of Channels: 1
• Amplifier Case Style: SOIC
• No. Of Pins: 24
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (18-Jun-2010)
• Package: RoHS Compliant
• Number Of Channels: 2
• Number Of Elements: 6
• Power Supply Requirement: Dual
• Common Mode Rejection Ratio: 20dB
• Voltage Gain Db: 54dB
• Input Resistance: 0.3@±5VMohm
• Input Bias Current: 27000@±5VnA
• Single Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (typ): ±5V
• Power Dissipation: 1.7W
• Rail/rail I/o Type: No
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 24
• Package Type: SOIC W
• Supply Voltage Range: ± 5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD604-EVALZ - BOARD EVAL FOR AD604 AMP
• Output Type: -
• Voltage - Supply, Single/dual (±): -
• Gain Bandwidth Product: -
• Voltage - Input Offset: -
• Lead Free Status / Rohs Status: Compliant

AD604
The 50 Ω termination resistor, in parallel with the 50 Ω source
resistance of the signal generator, forms an effective resistance of
25 Ω as seen by the input of the preamplifier, creating 4.07 μV of
rms noise at a bandwidth of 40 MHz. The noise floor of this
channel is consequently 6.5 μV rms, the rms sum of these two
main noise sources. The minimum detectable signal (MDS) for
this circuit is +6.5 μV rms (−90.7 dBm). Generally, the measured
signal should be about a factor of three larger than the noise
floor, in this case 19.5 μV rms. Note that the 25 μV rms signal
that this AGC circuit can correct for is just slightly above the
MDS. Of course, the sensitivity of the input can be improved by
band-limiting the signal; if the noise bandwidth is reduced by a
factor of four to 10 MHz, the noise floor of the AGC circuit with a
50 Ω termination resistor drops to +3.25 μV rms (−96.7 dBm).
Further noise improvement can be achieved by an input matching
network or by transformer coupling of the input signal.
The descriptions of the detector circuitry functions, comprising
a squarer, a low-pass filter, and an integrator, follow. At this
point, it is necessary to make some assumptions about the input
signal. The following explanation of the detector circuitry presumes
an amplitude modulated RF carrier where the modulating signal is
at a much lower frequency than the RF signal. The
multiplier functions as the detector by squaring the output signal
presented to it by the AD604. A low-pass filter following the
squaring operation removes the RF signal component at twice
Figure 46. Cascaded Gain Error vs. VGN (Based on Figure 44)
–10
–20
–30
90
80
70
60
50
40
30
20
10
–1
–2
–3
–4
4
3
2
1
0
0
Figure 45. Cascaded Gain vs. VGN (Based on Figure 44)
0.1
0.2
f
0.5
= 1MHz
0.7
0.9
1.2
1.3
VGN (V)
VGN (V)
1.7
1.7
f
= 1MHz
2.1
2.2
2.5
AD835
2.9
2.7
Rev. G | Page 20 of 32
the incoming signal frequency, while passing the low frequency
AM information. The following integrator with a time constant of
2 ms set by R8 and C11 integrates the error signal presented by
the low-pass filter and changes VG until the error signal is equal
to V
For example, if the signal presented to the detector is V1 = A ×
cos(ωt) as indicated in Figure 44, the output of the squarer is
−(V1)
circuitry is the necessity of providing negative feedback in the
control loop; actually, if V
control loop provides positive feedback. Squaring A × cos(ωt)
results in two terms, one at dc and one at 2ω; the following low-
pass filter passes only the −(A)
now forced equal to the voltage, V
squarer, together with the low-pass filter, functions as a mean-
square detector. As should be evident by controlling the value of
V
the AD835; if V
amplitude is ±400 mV.
Figure 47 shows the control voltage, VGN, vs. the input power at
frequencies of 1 MHz (solid line) and 10 MHz (dashed line) at
an output regulated level of 2 dBm (800 mV p-p). The AGC
threshold is evident at a P
power that can still be accommodated is about +3 dBm. At this
level, the output starts being distorted because of clipping in the
preamplifier.
As previously mentioned, the second preamplifier can be used
to extend the range of the AGC circuit in Figure 44. Figure 48
shows the modifications that must be made to Figure 46 to achieve
96 dB of gain and dynamic range. Because of the extremely high
gain, the bandwidth must be limited to reject some of the noise.
Furthermore, limiting the bandwidth helps suppress high-
frequency oscillations. The added components act as a low-pass
filter and dc block (C5 decouples the 2.5 V common-mode
output of the first DSX). The ferrite bead has an impedance of
about 5 Ω at 1 MHz, 30 Ω at 10 MHz, and 70 Ω at 100 MHz.
The bead, combined with R2 and C6, forms a 1 MHz low-pass
filter.
SET
Figure 47. Control Voltage vs. Input Power of the Circuit in Figure 44
, the amplitude of the voltage V1 can be set at the input of
SET
2
.
/1 V. The reason for all the minus signs in the detection
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
–80
–70
SET
equals −80 mV, the AGC output signal
1MHz
–60
–50
IN
SET
of about −79 dBm; the highest input
becomes greater than 0 V, the
–40
P
2
IN
/2 dc term. This dc voltage is
(dBm)
SET
–30
10MHz
, by the control loop. The
–20
–10
0
10