MCP6273T-E/MS Microchip Technology, MCP6273T-E/MS Datasheet - Page 17

• Manufacturer Part Number: MCP6273T-E/MS
• Description: IC OPAMP 2.0V SNGL CS R-R 8MSOP
• Manufacturer: Microchip Technology

Specifications of MCP6273T-E/MS

• Amplifier Type: General Purpose
• Number Of Circuits: 1
• Output Type: Rail-to-Rail
• Slew Rate: 0.9 V/µs
• Gain Bandwidth Product: 2MHz
• Current - Input Bias: 1pA
• Voltage - Input Offset: 3000µV
• Current - Supply: 170µA
• Current - Output / Channel: 25mA
• Voltage - Supply, Single/dual (±): 2 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• -3db Bandwidth: -

4.9.3
The MCP6275 provides the flexibility of Low power
mode for dual op amps in an 8-pin package. The
MCP6275 eliminates the added cost and space in a
battery powered application by using two single op
amps with Chip Select (CS) lines or a 10-pin device
with one CS line for both op amps. Since the two op
amps are internally cascaded, this device cannot be
used in circuits that require active or passive elements
between the two op amps. However, there are several
applications where this op amp configuration with a CS
line becomes suitable. The circuits below show
possible applications for this device.
4.9.3.1
With the cascaded op amp configuration, op amp B can
be used to isolate the load from op amp A. In
applications where op amp A is driving capacitive or
low resistive loads in the feedback loop (such as an
integrator or filter circuit) the op amp may not have
sufficient source current to drive the load. In this case,
op amp B can be used as a buffer.
FIGURE 4-10:
Buffer.
4.9.3.2
Figure 4-11
tion with Chip Select. Op amps A and B are configured
in a non-inverting amplifier configuration. In this
configuration, it is important to note that the input offset
voltage of op amp A is amplified by the gain of op amp
A and B, as shown below:
Therefore, it is recommended that you set most of the
gain with op amp A and use op amp B with relatively
small gain (e.g., a unity gain buffer).
© 2008 Microchip Technology Inc.
Where:
V
V
OSA
OSB
V
G
G
OUT
A
B
A
CASCADED OP AMP
APPLICATIONS
shows a cascaded gain circuit configura-
=
Load Isolation
Cascaded Gain
=
=
=
=
V
IN
MCP6275
G
op amp A gain
op amp B gain
op amp A input offset voltage
op amp B input offset voltage
A
CS
G
Isolating the Load with a
B
+
V
OSA
B
G
A
G
B
Load
+
V
OSB
V
OUTB
G
B
FIGURE 4-11:
Configuration.
4.9.3.3
Figure 4-12
amplifier with Chip Select. In this configuration, it is
recommended that well matched resistors (e.g., 0.1%)
be used to increase the Common Mode Rejection Ratio
(CMRR). Op amp B can be used to provide additional
gain and isolate the load from the difference amplifier.
FIGURE 4-12:
4.9.3.4
Figure 4-13
compensate for the non-ideal op amp characteristics
introduced at higher frequencies. This circuit uses
op amp B as a unity gain buffer to isolate the
integration capacitor C
capacitor with a low impedance source. Since both op
amps are matched very well, they provide a high quality
integrator.
FIGURE 4-13:
Compensation.
V
V
IN2
IN1
MCP6271/1R/2/3/4/5
V
IN
V
R
IN
4
R
R
R
2
2
R
1
shows op amp A configured as a difference
uses an active compensator (op amp B) to
1
Difference Amplifier
Inverting Integrator with Active
Compensation and Chip Select
R
A
3
R
A
1
A
MCP6275
Cascaded Gain Circuit
Difference Amplifier Circuit.
1
Integrator Circuit with Active
C
MCP6275
MCP6275
from op amp A and drives the
1
CS
CS
CS
R
2
R
4
DS21810F-page 17
R
B
B
1
R
B
3
V
V
OUT
OUT
V
OUT